Array substrate, display unit and control method thereof

A technology for array substrates and display devices, applied in static indicators, instruments, nonlinear optics, etc., can solve problems such as bad H-lines and affect display effects, and achieve the effect of reducing the width of the frame

Active Publication Date: 2015-05-27
BEIJING BOE OPTOELECTRONCIS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The embodiment of the present invention provides an array substrate, a display device and a control method thereof, which solves the technical problem of the H-line defect existing in the existing narrow-frame liquid crystal display and affects the display effect

Method used

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  • Array substrate, display unit and control method thereof
  • Array substrate, display unit and control method thereof
  • Array substrate, display unit and control method thereof

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Embodiment 1

[0034] Such as figure 1 As shown, the array substrate provided by the embodiment of the present invention can be used in a liquid crystal display, and the array substrate includes n gate line groups and n+1 main gate lines G1 to Gn+1. Wherein, each main gate line is connected to the gate driver of the liquid crystal display. Each gate line group includes adjacent first gate lines and second gate lines, a first pixel group is arranged corresponding to the first gate line, and a second pixel group is arranged corresponding to the second gate line. The first pixel group includes a plurality of first pixel units arranged in rows, each first pixel unit includes a first transistor T1; the second pixel group includes a plurality of second pixel units arranged in rows, and the second pixel unit includes a second transistor T2 and switching element T3. From figure 1 It can be seen from the figure that T1, T2 and T3 are correspondingly arranged in each column of pixel units of the li...

Embodiment 2

[0053] This embodiment is basically the same as Embodiment 1, the difference is: as image 3 As shown, in this embodiment, the n+1th main gate line Gn+1 is connected to the first main gate line G1. In this way, Gn+1 and G1 can be controlled together, and the timing diagram of G1 (that is, Gn+1) can be as follows Figure 4 As shown, in the two time periods before the first time period t1 in Embodiment 1, that is, within t2n-1 and t2n in the previous round of scanning, cooperate with Gn to realize the 2n-1th row and the 2nth row The pixel electrodes of the respective pixel units of the row are charged.

Embodiment 3

[0055] This embodiment is basically the same as Embodiment 1, the difference is that in this embodiment, the n+1th main gate line Gn+1 is merged into the first main gate line G1, that is, Gn+1 and G1 are combined is a main gate line as G1, then the gate (or source) of the third transistor T3 in the nth gate line group is still connected to the second gate line in the nth gate line group, but the nth gate line group The source (or gate) of T3 in the line set should be connected to G1. Specifically, it may be connected to the first gate line or the second gate line in the first gate line group.

[0056] In this way, the control method in Embodiment 2 can also be used. In addition, one busbar line can be further reduced. For example, in an HVGA liquid crystal display, only 120 busbar lines need to be arranged on both sides of the display area, which improves the symmetry of the lines on both sides of the display area.

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PUM

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Abstract

An array substrate, display device and control method thereof, the array substrate comprising a plurality of gate lines and data lines; the plurality of gate lines intersecting with the plurality of data lines define the pixels being arranged in an array; the plurality of gate lines comprise n number of gate line groups and n+1 number of primary gate lines (G1-Gn+1); each gate line group comprises a first gate line, and an adjacent second gate line, the first gate line being correspondingly provided with a first transistor (T1), and the second gate line being correspondingly provided with a second transistor (T2) and a switch element (T3); the first and second gate lines of an i-th gate line group are both connected to an i-th primary gate line (Gi); the gate electrode of the first transistor is connected to the first gate line, and a source electrode is connected to a corresponding data line (D), and a drain electrode is connected to a pixel electrode; the gate electrode of the second transistor is connected to one end of the switch element (T3) in the pixel unit, the source electrode is connected to the corresponding data line (D), and the drain electrode is connected to the pixel electrode; an (i+1)-th row primary gate line is connected to the other end of the switch element (T3) for controlling the switching on and off of the second transistor.

Description

technical field [0001] The invention belongs to the field of display technology, and in particular relates to an array substrate, a display device and a control method thereof. Background technique [0002] With the continuous development of display technologies, liquid crystal displays (Liquid Crystal Display, LCD) have occupied a dominant position in the field of flat panel displays. The pixels in the liquid crystal display are arranged in an array, and each pixel is generally divided into three pixel units of red, green, and blue. Each pixel unit is jointly controlled by a gate line and a data line. [0003] The number of grid lines in a liquid crystal display is equal to the number of rows of pixels. For example, in a common HVGA (Half-size video Graphics Array, half-video graphics array) type liquid crystal display, the number of pixels is 480×320, and 480 grid lines need to be set. Wire. These gate lines are to be connected to the gate driver from the side of the dis...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G02F1/1362G02F1/1368G02F1/133G09G3/36
CPCG09G3/3659G09G2310/021G02F1/13624G09G2320/0219G09G2300/0426G09G2310/0251G02F1/136286G02F1/1368G09G3/3677G09G2300/0814
Inventor 陈小川薛海林王磊李月李付强王学路
Owner BEIJING BOE OPTOELECTRONCIS TECH CO LTD
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