Latch up detection

Abstract

A device is presented. The device includes a first circuit coupled to first and second power rails of the device. The first circuit is subject to a latch up event in the presence of a latch up condition. The latch up event includes a low resistance path created between the first and second power rails. The device also includes a latch up sensing (LUS) circuit coupled to the first circuit. The LUS circuit is configured to receive a LUS input signal from the first circuit and generates a LUS output signal to the first circuit. When the input signal is an active latch up signal which indicates the presence of a latch up condition, the LUS circuit generates an active LUS output signal which creates a break in the low resistance path to terminate the latch up event.

Description

technical field [0001] This disclosure is directed to providing resilient and tight latch design rules Background technique [0002] In integrated circuits (ICs), latch-up can occur in four-layer pnpn structures. The pnpn structure contains bipolar transistors. Under abnormal conditions, the bipolar transistor may be triggered by a trigger stimulus, such as a positive or negative voltage spike or a positive or high negative current on an input or output pin of an integrated circuit or a power pad. Pressure (current-forcing), and open. If the product of the gains of the transistors in the feedback loop is large enough (eg, b1xb2 is greater than 1) to sustain regeneration, a non-ideal current path will result in a pnpn configuration. There is a large amount of current that can pass through the pnpn structure and cause latch-up. For example, large amounts of current can flow from a power supply or I / O pad to ground. Latch-up can cause circuit malfunction and / or irreversibl...

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Problems solved by technology

These design rules are relatively large and inelastic

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