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Multi-Gate FETs and methods for forming the same

A gate electrode, gate dielectric technology, applied in the field of multi-gate FET and its formation, can solve problems such as disadvantage and lowering the threshold voltage of FinFET

Active Publication Date: 2014-01-22
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this approach leads to the introduction of corresponding dopants into the silicon fins located above the silicon strips, which is disadvantageous
Therefore, the threshold voltage Vth of the corresponding FinFET is lowered

Method used

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  • Multi-Gate FETs and methods for forming the same
  • Multi-Gate FETs and methods for forming the same
  • Multi-Gate FETs and methods for forming the same

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Embodiment Construction

[0027] The manufacture and use of the embodiments of the present invention are discussed in detail below. However, it should be understood that the embodiments provide many applicable inventive concepts that can be implemented in various specific environments. The specific embodiments discussed are only exemplary and are not used to limit the scope of the present invention.

[0028] A method of forming a fin field effect transistor (FinFET) is provided. The intermediate stage of manufacturing FinFET according to the embodiment is shown. Discuss the variation of the embodiment. In the various views and exemplary embodiments throughout the text, the same reference numbers are used to denote the same elements.

[0029] Figure 1 to Figure 6B A cross-sectional view of a FinFET formed according to some embodiments is shown. Reference figure 1 , Form a structure. The structure shown includes a portion of a wafer 10 which further includes a substrate 20. The substrate 20 may be a si...

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Abstract

The present invention provides a multi-Gate FETs and methods for forming the same. A method includes oxidizing a semiconductor fin to form an oxide layer on opposite sidewalls of the semiconductor fin. The semiconductor fin is over a top surface of an isolation region. After the oxidizing, a tilt implantation is performed to implant an impurity into the semiconductor fin. The oxide layer is removed after the tilt implantation.

Description

Technical field [0001] The present invention relates to semiconductor manufacturing, in particular, to a multi-gate FET and a method of forming the same. Background technique [0002] As integrated circuits continue to scale down and the requirements for integrated circuit speed continue to increase, transistors need to have higher drive currents and continuously reduced sizes. Therefore, fin field effect transistors (FinFETs) were developed, also known as multi-gate FETs. A typical FinFET includes a semiconductor fin above the substrate, which is used to form the channel region of the FinFET. The channel region includes the sidewall portion and sometimes the top surface portion of the semiconductor fin. When the channel region includes the sidewall portion but not the top surface portion, the corresponding FinFET is called a dual-gate FinFET. When the channel region includes a sidewall portion and a top surface portion, the corresponding FinFET is called a tri-gate FinFET. [...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L21/28H01L29/78H01L29/423
CPCH01L21/2652H01L21/02164H01L21/02236H01L21/02255H01L21/26513H01L21/26586H01L21/31111H01L21/76224H01L21/823431H01L21/823481H01L27/0886H01L29/0649H01L29/0653H01L29/0847H01L29/66803H01L29/66818H01L29/7851H01L29/7853H01L29/7854
Inventor 卢文泰
Owner TAIWAN SEMICON MFG CO LTD