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An ultra-high-speed digital configurable frequency divider

A frequency divider and digital technology, applied in the direction of electrical components, automatic power control, etc., can solve problems such as unfavorable frequency division ratio configuration, and achieve the effect of small circuit resource overhead

Active Publication Date: 2016-03-02
CHENGDU ANALOG CIRCUIT TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In some high-speed designs, prescaler circuits are used, but the prescaler circuits are generally fixed, which is not conducive to the configuration of the frequency division ratio.
Some divide ratios up to 2 20 High-speed configurable frequency dividers with or higher frequency division ratios pose new challenges to the design of frequency dividers

Method used

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  • An ultra-high-speed digital configurable frequency divider
  • An ultra-high-speed digital configurable frequency divider

Examples

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Embodiment Construction

[0010] figure 1 Middle: FEQ_I is the signal for the previous stage to judge whether the count value is equal to the frequency division ratio. CI is the carry flag signal of the previous stage of the serial counter. HEQ_I is the signal for the previous stage to judge whether the count value is equal to half of the frequency division ratio. SET is the setting terminal of the frequency division counter. FC is one of the frequency division ratio values. CK is a high frequency clock. CLR is the clearing terminal of the frequency division counter. HC is one of half of the frequency division ratio. FEQ_O is the signal output for judging whether the count value is equal to the frequency division ratio at present. CO is the carry flag output of the current count. HEQ_O is a signal for currently judging whether the count value is equal to half of the frequency division ratio.

[0011] figure 2 Middle: CELL1-CELLN is figure 1 The basic unit in . DIVN is the frequency division...

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Abstract

An ultra-high speed digital configurable frequency divider comprises N cascaded configurable frequency divider basic units, one OR gate OR1 connected with the Nth configurable frequency divider basic unit and a flap-flop DFF0 connected with the OR gate OR1. The ultra-high speed digital configurable frequency divider is an N-bit configurable frequency divider, and the frequency dividing number of the ultra-high speed digital configurable frequency divider is configurable in a 2N-2N range, wherein the N is an integer larger than 1. The frequency dividing ratio of the ultra-high speed digital configurable frequency divider is configurable in the 2N-2N range, and thus the speed of the ultra-high speed digital configurable frequency divider barely increases along with the increase of the N.

Description

technical field [0001] The invention relates to a digital frequency divider, in particular to an ultra-high-speed digital configurable frequency divider. Background technique [0002] Frequency divider is the basic module of digital circuit design, and it is widely used in digital circuit design. In digital circuit design, a digital counting frequency divider is often used to generate sub-clocks in a multi-clock system, and the feedback clock in a phase-locked loop multiplier circuit is also generated by a frequency divider. [0003] The frequency divider converts the high-frequency clock signal into a low-frequency clock signal output, including fixed frequency dividers and configurable frequency dividers (programmable frequency division). In a circuit with a high system clock, if the frequency division ratio is not too large, it can be realized by using a shift counting frequency divider. The advantage of shift counting frequency division is that the speed can be very hi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03L7/18
Inventor 不公告发明人
Owner CHENGDU ANALOG CIRCUIT TECH INC