An error correction circuit for sram memory

An error correction circuit and memory technology, applied in static memory, instruments, etc., can solve the problems of device layout and wiring complexity, increased device power consumption, increased circuit area overhead, etc.

Active Publication Date: 2017-08-29
北京中科微投资管理有限责任公司
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  • Abstract
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AI Technical Summary

Problems solved by technology

[0004] At present, the following methods are mainly used to solve the SMU problem of the memory: one is to strengthen the process at the device level, the other is to physically disperse the logic adjacent bits, and the third is to use the BISC+SEC-DED method to implement multi-bit For error correction, the fourth is to detect and correct multiple bit errors through coding methods. The first three methods all require protection design at the device level, which brings complexity in device layout and wiring, increases device power consumption, and at the same time Increased production cost of the device
like figure 1 As shown, the existing shortened Hamming code encoding circuit is separated from the decoding circuit, which increases the overhead of the circuit area
On the other hand, SRAM cannot read and write at the same time, resulting in the independence of the encoding circuit and decoding circuit, which cannot improve the reading and writing speed.

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  • An error correction circuit for sram memory
  • An error correction circuit for sram memory

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Embodiment Construction

[0021] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and understandable, the specific implementation modes of the present invention will be described in detail below in conjunction with the accompanying drawings, so that the above-mentioned and other purposes, features and advantages of the present invention will be clearer. Like reference numerals designate like parts throughout the drawings. The drawings have not been drawn to scale, emphasis instead being placed upon illustrating the gist of the invention.

[0022] Such as figure 2 As shown, the present invention provides an error correction circuit for SRAM memory, which includes: an encoding module Encoder, a first transmission gate module TG, a second transmission gate module and an exclusive OR operation module TG&XOR, and an error correction circuit module Locating error.

[0023] In this embodiment, the input end of the encoding module Encoder is connect...

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Abstract

The invention provides an error correction circuit of an SRAM (Static Random Access Memory)-type memory. The error correction circuit comprises an encoding module, a first transmission gate module, a second transmission gate module, an exclusive or operational module and an error correcting circuit. The encoding module is used for performing a decoding operation, a control signal is added and time division multiplexing (TDM) is performed on encoding and decoding operations, so that the circuit area is small, meanwhile the reading and writing time of the memory is quickly, and the error correction is accurate.

Description

technical field [0001] The invention relates to memory data reliability, in particular to a circuit for ensuring reliability of memory read and write data. Background technique [0002] It is well known that high-energy particles in the space radiation environment can cause transient errors in multiple units inside the VLSI device. In SRAM memory, the performance of such transient errors in multiple units is multi-bit flipping. Since the particle distribution in the space environment has the characteristics of high energy and low flux, the multi-bit flip of the memory is mainly due to the single high-energy particle hitting the sensitive area of ​​the device, and the charge generated is diffused, causing multiple units of the device to appear instantaneous. mistake. [0003] With the continuous development of the integrated circuit manufacturing process, the process size of the SRAM structure device is continuously reduced, and the core voltage is continuously reduced, so t...

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Application Information

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Patent Type & AuthorityPatents(China)
IPC IPC(8): G11C29/42
Inventor刘鑫赵发展韩郑生
Owner北京中科微投资管理有限责任公司