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Tile-based interleaving and deinterleaving for digital signal processing

A technology of digital signal processing and area, applied in the direction of electric digital data processing, coding, instrument, etc.

Active Publication Date: 2016-10-26
IMAGINATION TECH LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Each DRAM only has a limited number of pages open at a time (typically four pages), and opening a page to access data requires many overhead cycles

Method used

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  • Tile-based interleaving and deinterleaving for digital signal processing
  • Tile-based interleaving and deinterleaving for digital signal processing
  • Tile-based interleaving and deinterleaving for digital signal processing

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Embodiment Construction

[0027] The embodiments are described below by way of example only. These examples represent the best way currently known to applicants to put these embodiments into practice, although these best modes are not the only ways in which the invention can be practiced. The description gives the functionality of the example and the sequence of steps used to construct and operate the example. However, the same or equivalent functions and sequences can be implemented by different examples.

[0028] The following describes a digital signal processing system utilizing a general-purpose digital signal processor (DSP) as well as dedicated hardware peripherals. To use memory efficiently, different elements of the system can access shared on-chip memory. A transfer engine such as a direct memory access (DMA) controller can write data items to and read data items from on-chip memory. On-chip memory includes static random access memory (SRAM), and the transfer engine also has a port to dyna...

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Abstract

Describes tile-based interleaving and deinterleaving of row-column interleaved data. In one example, deinterleaving is divided into two memory transfer stages, the first stage from on-chip memory to DRAM, and the second stage from DRAM to on-chip memory. Each stage operates on a portion of the row-column interleaved data block and reorders these data items so that the output of the second stage includes the deinterleaved data. In the first phase, data items are read from the on-chip memory according to a non-linear memory read address sequence and written to the DRAM. In the second stage, data items are read from DRAM according to bursts of a linear address sequence, which efficiently utilizes the DRAM interface, and written back to on-chip memory according to a non-linear memory write address sequence.

Description

Background technique [0001] Digital signal processing finds use in a wide variety of applications. Many of these applications are real-time in the sense that there are time constraints on the processing of data in order for it to be meaningful or useful to the end user. An example of this is digital broadcast streams such as digital television and digital radio. A data signal processing system needs to be able to process and decode a live stream fast enough so that data can be output as quickly as it was received (unless buffered). [0002] DSP systems typically use one or more specialized hardware peripherals in addition to a more general-purpose digital signal processor. These hardware peripherals are processing modules designed to perform specific signal processing tasks in a fast and efficient manner. For example, interleaving and deinterleaving are operations typically performed on real-time data using hardware peripherals. Interleaving and deinterleaving are memory-i...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/16G06F13/20G06F13/28
CPCH03M13/2707H03M13/276H03M13/6505G06F12/0607
Inventor P·默林A·J·安德森M·厄尔-哈加
Owner IMAGINATION TECH LTD