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Low Supply Voltage Switching Architecture

一种开关、模拟电压的技术，应用在电子开关架构领域

Active Publication Date: 2018-06-12
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If the sampling signal is asynchronous to the ADC clock, it can cause feedback at the input before sampling

Method used

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  • Low Supply Voltage Switching Architecture
  • Low Supply Voltage Switching Architecture
  • Low Supply Voltage Switching Architecture

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0019] able to solve figure 2 and image 3 A sample of at least some of the problems with CMOS switching circuits in CMOS switching circuits 50 is in Figure 4 The figure in the middle is shown, which is now used as a reference. exist Figure 4 In the sampled CMOS switching circuit 50 of the present invention, first and second series-connected NMOS switching devices 52 and 54 are connected between the input node 38 and the output node. The first and second NMOS switching devices 52 and 54 may have threshold voltages.

[0020] The sampling signal SAMP is connected to the gates of the first and second NMOS devices 52 and 54 . The sampling signal SAMP has a voltage value equal to VDD and operates to turn on the first and second NMOS switching devices 52 and 54 when a positive voltage is applied to their gates.

[0021] A pair of series-connected extended-drain p-channel metal-oxide-semiconductor (DEPMOS) devices 56 and 58 are connected in a “T” configuration between input n...

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Abstract

The invention discloses a low power supply voltage switching architecture. The sampling CMOS switch includes first and second NMOS devices connected in series between input and output nodes. The first and second NMOS devices are activated by the sampling signal. A pair of low-voltage DEPMOS devices are connected in a T-structure between the input and output nodes. Low-voltage DEPMOS devices are activated by an inverted sampling signal. The feedback circuit includes a DEPMOS device and a third high voltage NMOS device and a current source. The third NMOS device is controlled by the signal of the input node. The switch switchably connects the analog voltage source with the source of the third NMOS device and the gate of the DEPMOS device according to the phase of the inverted sampling signal. The configuration of the sampling CMOS switch can protect the gate oxide insulation of the low voltage DEPMOS transistor from high voltage damage.

Description

technical field [0001] The various circuit embodiments described in this disclosure relate generally to electronic switches, and more particularly to electronic switch architectures that can operate at low supply voltages. Background technique [0002] Electronic switches are used in many electronic products. An example of an analog-to-digital converter (ADC) is one application that makes extensive use of electronic switches. There are many other general applications as well. An example of a complementary metal oxide (CMOS) switch 10 for electronic switching is in figure 1 is shown for reference. [0003] Switch 10 includes a p-channel metal oxide semiconductor (PMOS) device 12 and an n-channel metal oxide semiconductor (NMOS) device 14 . PMOS device 12 has its source connected to input node 16 and its drain connected to output node 18 . The gate of the PMOS device 12 is connected to a reference voltage, or ground 22 . NMOS device 14 has its drain connected to input no...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K17/687
CPCH03K17/04123H03K17/102H03K2217/0009H03K2217/0054H03K17/6871
Inventor V·米什拉R·希纳卡兰
Owner TEXAS INSTR INC