Hybrid dram memory and method for reducing power consumption when the dram memory is refreshed

Abstract

The invention discloses a mixed DRAM storage and method of reducing refresh power consumption of the DRAM storage. A non-volatile storage is combined with a DRAM main storage, a specified storage cell of the non-volatile storage is used to replace a tail end storage cell of the DRAM main storage, so that a refresh cycle is greatly improved, refresh rate is reduced, and refresh power consumption of the DRAM main storage is reduced greatly.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices and integrated circuits, in particular to a hybrid DRAM memory and a method for reducing power consumption when the DRAM memory is refreshed. Background technique [0002] Over the past few decades, the cost of dynamic random access memory (DRAM) has continued to decrease with Moore's Law. However, as the feature size becomes smaller and smaller, the power consumption requirements of the chip are also higher and higher. Due to the leakage of the DRAM storage capacitor, it must be refreshed every once in a while, and the power consumption of the refresh is increased. For example, figure 1 As shown, the refresh power consumption of a DRAM with a smaller capacity will be lower, accounting for only a small part of the power consumption. However, as the DRAM capacity increases, the refresh power consumption will increase significantly. This is because the feature size shrinks and the powe...

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Problems solved by technology

However, this structure has very high requirements on the process and increases the cost, and the DRAM still needs to be refreshed regularly, and the refresh power consumption has not been reduced.

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