A low-power refresh method based on block dram

Abstract

The invention provides a low-power-consumption refreshing method based on a block DRAM (dynamic random access memory). The low-power-consumption refreshing method comprises the steps that when the DRAM is in a busy state, the refreshing period of the DRAM is T_refresh0; when the DRAM is in a non-busy state, certain retaining time T_refresh1 of N blocks in a DRAM chip is selected, and the T_refresh1 is longer than the T_refresh0; under the retaining time T_refresh1, L blocks with worst storage units are respectively recorded as blocks from L_0 to L_L-1 (L is larger than 0 and less than or equal to N); the L blocks in the DRAM chip are closed, and the refreshing period time of (N-L) blocks is prolonged to T_refresh1. According to the technical scheme disclosed by the invention, the refreshing period of the block DRAM can be effectively prolonged, the refreshing power consumption is greatly reduced, and the performance of the DRAM is basically not affected.

Description

technical field [0001] The invention belongs to the field of computer hardware, and relates to a memory bar refresh method, in particular to a low-power refresh method based on block DRAM. Background technique [0002] As feature sizes get smaller, dynamic random access memory (DRAM) chips are increasingly demanding power consumption. Due to the leakage of the DRAM storage capacitor, it must be refreshed every once in a while. As the capacity of the DRAM increases, the power consumption of the refresh is also increasing. For example, figure 1 shown. Refresh operations not only consume power, but also degrade DRAM performance due to interference with memory accesses. At present, the DRAM refresh frequency is determined by the worst storage unit (tail bit), for example, 64ms, and the storage unit retention time distribution is as follows figure 2 As shown in the figure, it can be seen from the figure that the ability of most cells to hold data is much longer than the refre...

AI Technical Summary

Problems solved by technology

Since DRAM is only used as a cache, the capacity does not need to be large, and PCM does not need to be refreshed regularly when storing data as the main storage medium, so this structure can greatly reduce the power consumption of data storage, but because PCM storage and access speeds are slow, so This structure has a significant drop in overall performance

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