Test Structure and Test Method for Reliability Analysis of Interlayer Dielectric

Abstract

The invention provides a test structure and a test method for reliability analysis on interlayer dielectric. The test structure at least comprises a polysilicon structure and an insulation medium structure formed on a substrate, a first contact line structure, a first metal bar structure, a second contact line structure, a second metal bar structure and the interlayer dielectric. The test structure can rapidly and effectively detect reliability of the interlayer dielectric between the polysilicon structure below a metallization layer and a contact line, the test structure and a tested integrated circuit device on a wafer are formed together without extra mask plates; the test structure is compatible with an integrated circuit in design and follows the minimum design criterion of the integrated circuit, the test structure is in consistent with the integrated circuit in design dimensions, so reliability of the interlayer dielectric in a device can be really reflected; the test structure can be formed at a cutting line of the wafer and does not occupy the area of a chip for formation of the integrated circuit device.

Description

technical field [0001] The invention belongs to the field of integrated circuits, and relates to a structure and a method for testing the reliability of an interconnection structure, in particular to a test structure and a test method for reliability analysis of an interlayer dielectric. Background technique [0002] Integrated circuits have grown from a handful of interconnected devices fabricated on a single silicon chip to millions of devices. Conventional integrated circuits offer performance and complexity far beyond what was originally imagined. To increase complexity and circuit density (i.e., the number of devices that can be packed into a given chip area), the smallest device feature size (also called device "geometry") has become smaller and smaller with each generation of integrated circuits. smaller. [0003] Because every process used in integrated circuit fabrication has limitations, making devices smaller is very challenging. In integrated circuits, shallow...

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Problems solved by technology

[0006] For the reliability test of the interlayer dielectric between the polysilicon structure (poly) and the contact line (contact), it cannot be tested in the chip yield test (Circuit Probing) at present, because the chip yield test can only pass the functional test. Functional problems (such as accidental conduction) that affect the operation of the chip are detected. Therefore, the reliability of the interlayer dielectric can only be verified based on the product-level reliability test (Product ReliabilityTest), that is, testing the packaged wafer. Not only time consuming but also costly

[0007] In order to reduce cost and time consumption, most of the existing test structures adopt process-level reliability test (ProcessReliabilityTest). For example, the patent (application number: CN200810033131.4) is to test the interlayer dielectric between the metal strips in the metallization layer. Reliability test, but this test structure cannot be used for reliability test of the interlayer dielectric between the polysilicon structure and the contact line under the metallization layer, in other words, the existing wafer level reliability test (WaferLevelProcessReliabilityTest) , the reliability of the interlayer dielectric located under the metallization layer cannot be tested, wherein the interlayer dielectric is the interlayer dielectric located between the polysilicon structure (poly) and the contact line (contact), and the polysilicon structure and contact lines are located under the metallization layer

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