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Method for fabricating self-aligned double-layer patterned semiconductor structure

A manufacturing method and semiconductor technology, applied in the fields of semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of self-aligned double-layer pattern structure morphology and dimensional instability, etc.

Active Publication Date: 2017-07-11
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Because the silicon oxide layer 16 remaining on both sides of the core pattern layer 13 is inclined, its shape affects the shape of the self-aligned double-layer pattern structure, so that the shape and shape of the self-aligned double-layer pattern structure dimensionally unstable

Method used

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  • Method for fabricating self-aligned double-layer patterned semiconductor structure
  • Method for fabricating self-aligned double-layer patterned semiconductor structure
  • Method for fabricating self-aligned double-layer patterned semiconductor structure

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Embodiment Construction

[0037] In the prior art, when the core pattern layer is etched with the photoresist layer as a mask, since the material of the core pattern layer is amorphous carbon, in order to ensure that the core pattern layer and the silicon nitride layer below and the hard layer above Etch selectivity between mask layers, using SO 2 and O 2The mixed gas is used as the etching gas, and the shape of the sidewall of the finally formed core pattern layer is inclined, and the core pattern layer formed above the silicon nitride layer presents a positive trapezoidal shape, which also leads to The inclined morphology of the silicon oxide layer on both sides of the core pattern layer finally makes the size and shape of the self-aligned double-layer pattern formed by using the silicon oxide layer on both sides of the core pattern layer as a mask unstable.

[0038] In order to solve the above problems, the present invention provides a method for fabricating a self-aligned double-layer patterned se...

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Abstract

The invention provides a manufacturing method of a self-aligned two-layer graph semiconductor structure. The manufacturing method includes the steps that a semiconductor substrate is provided, and a first silicon oxide layer and a silicon nitride layer are formed on the semiconductor substrate; a core graph layer is formed on the silicon nitride layer and made of polycrystalline silicon; an antireflection layer and a photoresist layer are sequentially formed on the core graph layer, and a core graph is defined by the photoresist layer; with the photoresist layer as a mask, etching is conducted on the antireflection layer and the core graph layer, patterns of the core graph are transferred onto the core graph layer, the core graph layer left on the silicon nitride layer has vertical morphology, and second silicon oxide layers with vertical appearance are formed on the two sides of the left core graph layer; with the second silicon oxide layers with the vertical appearance as masks, etching is conducted on the silicon nitride layer and the first silicon oxide layer to form the self-aligned two-layer graph structure with vertical appearance.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for manufacturing a self-aligned double-layer pattern semiconductor structure. Background technique [0002] At the node of 20nm and below, self-aligned double-layer patterning (SADP) process has been applied to the production of key semiconductor layers such as active area (AA) and polysilicon (Poly). [0003] Please refer to Figure 1-Figure 7 A schematic cross-sectional structure diagram of a method for fabricating a self-aligned double-layer patterned semiconductor structure in the prior art is shown. Please refer to figure 1 , firstly, a semiconductor substrate 10 is provided, and a silicon nitride layer 11, a core pattern layer 13, a hard mask layer 17, an antireflection layer 14 and a photoresist layer 15 are sequentially formed on the semiconductor substrate 10, and the core The pattern layer 13 is made of amorphous carbon (APF), and the hard mask layer...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/02H01L21/033
CPCH01L21/0274H01L21/0332
Inventor 崇二敏黄君
Owner SHANGHAI HUALI MICROELECTRONICS CORP