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How to deal with the timing interleaving problem of the timer when measuring the frequency with the cycle measuring method

A technology for measuring frequency and processing method, which is applied in the field of processing the timing interleaving problem of timers when measuring frequency with cycle measurement method, which can solve problems such as strong interference fluctuations, and achieve the effect of avoiding carry

Active Publication Date: 2017-02-22
XIAN AERO ENGINE CONTROLS
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The resulting system, while functioning normally most of the time, has occasional fluctuations resembling strong disturbances

Method used

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  • How to deal with the timing interleaving problem of the timer when measuring the frequency with the cycle measuring method
  • How to deal with the timing interleaving problem of the timer when measuring the frequency with the cycle measuring method
  • How to deal with the timing interleaving problem of the timer when measuring the frequency with the cycle measuring method

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Embodiment 1

[0046] refer tofigure 1 , the hardware background in this embodiment is: multi-stage cascading of timers, without hardware capture function. use figure 1 In the process shown, the read high and low data of the timer completely avoids the situation of interspersed carry and ensures the correct length of the subsequent calculation cycle. The selection of the limit X should ensure that: if the condition in c) is not satisfied, no timer carry will occur between a) and b). Among them, "high bits at all levels" means that if the timers are cascaded to more than two levels, they are collectively referred to as "high bits at all levels" except for the lowest level.

[0047] In this case, the method for dealing with the timing interleaving problem of the timer when measuring the frequency by the cycle measurement method includes the following steps:

[0048] a) Read the high-order timer;

[0049] b) read the low timer;

[0050] c) If the read value of the low-order timer is less th...

Embodiment 2

[0052] refer to figure 2 , the hardware background in this embodiment is: multi-stage cascading of timers, and its low bits have hardware capture functions. Used in the capture interrupt routine figure 2 In the flow shown, when there is a possibility of a carry immediately after the capture time, the final high value of the timer obtained is actually the value before the capture, which also completely avoids the interspersed carry and ensures the correct length of the subsequent calculation cycle .

[0053] In this case, the method for dealing with the timing interleaving problem of the timer when measuring the frequency by the cycle measurement method includes the following steps:

[0054] a) Take the capture value as the low bit of this timing value, and this step can also be moved to any moment before the low bit of this timing value is used later;

[0055] b) Read the high-order timer and temporarily use it as the high-order value of this timing value;

[0056] c) re...

Embodiment 3

[0063] refer to image 3 , the hardware and software background in the present embodiment is: the timer has a hardware capture function, and when the timer overflows, an interrupt can be generated, and the variable V is incremented in the timer overflow interrupt service routine. Used in the capture interrupt program (interrupts are turned off when entering) image 3 The flow shown obtains V and vbak for use below. When there is a possibility that the timer is full and overflows immediately before and after the capture time, it can be guaranteed that the finally obtained vbak is actually the theoretical value before capture, and also completely avoids the occurrence of errors due to timing interleaving.

[0064] In this case, the method of dealing with the timing interleaving problem of the timer when measuring the frequency by the cycle measurement method, the operation of reading the current timing value in the capture interrupt includes the following steps:

[0065] a) Fo...

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Abstract

It is a method to overcome possible errors caused by timing interleaving of software's reading action of timer and timer's carry, overflow, and interrupt and capture when measuring frequency by cycle measurement method. Aiming at various hardware backgrounds, adopt the method of reasonably arranging the operation sequence and logical judgment to avoid interspersed events such as timer carry and overflow that hinder the correctness of the result in the middle of the formal read operation of the timer, so as to ensure the obtained The timing value was completely correct at that time.

Description

[0001] Technical field [0002] The invention relates to a method for avoiding possible errors caused by the timing interleaving of the system's reading action of the timer and the timing interleaving of the timer's carry, overflow, interrupt and capture when the frequency is measured by the cycle measurement method. Background technique [0003] In the microcomputer-based industrial control system, there are usually two methods of direct frequency measurement and cycle measurement for frequency measurement. Among them, the cycle measurement method is to measure the length of the cycle, and its reciprocal represents the frequency. The cycle measurement method is superior to the direct frequency measurement method in terms of delay and accuracy. However, there are some technical details in the week measurement method that need to be considered. One of the problems is the timing interleaving of several events when reading timer information. [0004] The general basic algorithm...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/22G06F11/26
Inventor 郝立中龚新平许奉亮燕洁静周彩霞朱旭
Owner XIAN AERO ENGINE CONTROLS
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