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Operation method of nand array and computer-readable non-transitory storage medium

A method of operation, non-transitory technology, applied in the field of non-transitory storage media

Active Publication Date: 2017-11-17
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] Regardless of hot carrier injection, program disturb remains a problem in high-density memories

Method used

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  • Operation method of nand array and computer-readable non-transitory storage medium
  • Operation method of nand array and computer-readable non-transitory storage medium
  • Operation method of nand array and computer-readable non-transitory storage medium

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Experimental program
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Embodiment Construction

[0092] The detailed description of the embodiments is provided with reference to the accompanying drawings.

[0093] figure 1 It is a functional layer block diagram of a data processing system 100 incorporating a memory (such as a high-capacity 3D NAND flash array 150). The memory can also be various NAND flash, NOR flash, or any suitable memory device with erase blocks. The memory can be physically divided into multiple sections, so that each physical section is the minimum size unit for the block erase operation supported by the memory. An erased block of memory may correspond to one or more physical sectors. For example, the capacity of each physical section of the memory may be 16KB. In some examples, an erased block of the memory 150 may include a physical sector, and have the same capacity of 16KB as the physical sector, or a plurality of physical sectors, for example, 4 physical sectors have a total capacity of 64KB. capacity, or 8 physical sections with a total cap...

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Abstract

The present invention discloses an operation method of an NAND array and a computer readable non-transient storage media, which are technologies supporting a nonvolatile memory and reducing the programming interference. A three-dimensional or two-dimensional NAND array comprises a plurality of pagings divided into a plurality of paging sets. A storage unit is allowed to be stored in a first paging set of the plurality of paging sets in an erasing area of the three-dimensional NAND array, but the storage of the storage unit which is stored in a second paging set of the plurality of paging sets in the erasing area of the three-dimensional or two-dimensional NAND array is minimum. The pagings in the same paging set are not adjacent to each other in the three-dimensional or two-dimensional NAND array.

Description

technical field [0001] The present invention relates to a memory device and system including memory management, especially a method for operating a NAND array and a computer-readable non-transitory storage medium. Background technique [0002] Flash memory is a type of non-volatile integrated circuit memory technology. Traditional flash memory uses floating gate memory cells. As the density of memory devices increases and floating gate memory cells become closer together, interference between charges stored in adjacent floating gates becomes a problem. This limits the ability to increase the density of flash memory based on floating gate memory cells. Another type of memory cell used in flash memory may be referred to as a charge trapping memory cell, which uses a dielectric charge trapping layer instead of a floating gate. [0003] A typical flash memory cell consists of a field effect transistor FET structure having a source and drain separated by a channel, and a gate ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/04G11C16/10G11C16/34
Inventor 张育铭李永骏卢星辰李祥邦王成渊张原豪郭大维
Owner MACRONIX INT CO LTD