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A clock synchronization method and device
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A clock synchronization and clock end technology, applied in synchronization devices, digital transmission systems, electrical components, etc., can solve problems such as register overflow and inability to obtain frequency difference values, and achieve the effect of improving efficiency and reducing algorithm complexity.
Active Publication Date: 2017-12-08
RAISECOM TECH
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However, in various fitting algorithms, if the clock accuracy is higher in nanoseconds, then a larger register space is often required for the fitting algorithm, especially in the process of multiplying large numbers, due to the effective digits below seconds Up to 9 decimal integers, corresponding to the binary number is generally 30 bits, so for the common 32-bit system, use the largest data type unsign long to save, and the multiplication operation involved in the fitting process will inevitably cause register overflow, which also Unable to get a more accurate frequency difference value
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Embodiment 1
[0048] This embodiment provides a clock step synchronization method, the principle of which is as follows figure 1 As shown, the Master Clock is the main clock, the Slave Clock is the slave clock, and both the Master Clock and the Slave Clock are nanosecond-level clocks. The frequency synchronization method based on the above-mentioned Master Clock and the Slave Clock is as follows figure 2 shown, including the following steps:
[0049] Step 2001, in the process of clock synchronization, set the time interval (exemplarily periodically) to be sent by the Master end with the sending time stamp t 0 Sync synchronization message;
[0050] Step 2002, after the Slave end receives the Sync synchronization message, record the time stamp t of the arrival of the Sync synchronization message 1 ;
[0051] Step 2003, the Slave end will receive the time stamp t corresponding to the time of the Sync synchronization message 1 Subtract the time stamp t corresponding to the sending time car...
Embodiment 2
[0075] This embodiment provides a clock synchronization device that can implement the method in Embodiment 1 above. The device includes at least a first storage unit, a computing unit, and a synchronization processing unit, wherein:
[0076] The first storage unit stores the time stamp t of the synchronization message sent by the main clock end 0 , and the delay value ΔT=t introduced by the transmission of the synchronization message to the slave clock terminal 1 -t 0 , where the t 1 is the time stamp of receiving the synchronization message from the clock terminal, the t 1 and ΔT are nanosecond timestamp data;
[0077] computing unit, according to t 1 and ΔT, use the first-order curve to fit and determine the frequency difference k, where, when determining the frequency difference K, for t 1 Do multiplication calculation with ΔT, split the multiplier in the multiplication calculation into high 16-bit content and low 16-bit content, and split the multiplicand into high 16...
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Abstract
The invention discloses a clock synchronization method and device, and relates to clock synchronization technology. The method of the present invention includes: when the set time interval arrives, the master clock end sends a synchronous message carrying a transmission time stamp t0, the slave clock end records the time stamp t1 of the arrival of the synchronous message, and calculates the time stamp introduced by the transmission network Delay value ΔT=t1‑t0; according to t1 and ΔT, determine the frequency difference k to adjust the frequency of the slave clock to achieve master-slave clock synchronization; where the nanosecond time stamp t1 and ΔT are multiplied, and the multiplication operation The multiplier and multiplicand are divided into high 16-bit content and low 16-bit content respectively; multiplication calculations are performed on the high and low 16-bit content of the multiplier and multiplicand, and the calculation results are added to obtain 64 The final product of bits. The invention also discloses a clock synchronization device. The technical solution of the present application reduces algorithm complexity and improves calculation efficiency.
Description
technical field [0001] The invention relates to clock synchronization technology, in particular to a clock synchronization method and device. Background technique [0002] With the development of network technology, the accuracy of time synchronization is getting higher and higher. Some services even require the time synchronization accuracy between base stations to be within tens of nanoseconds. At present, great breakthroughs have been made in hardware technology, and the precision of time stamps carried by packets transmitted in the network has reached the nanosecond level. In addition, the formulation and release of the IEEE1588 Precision Time Synchronization Protocol (PTP) provides a behavioral standard for using high-precision time stamps to achieve clock synchronization. All of the above conditions ensure the possibility of clock synchronization between devices at the nanosecond level. [0003] To achieve high-precision synchronization between the two clocks, the ca...
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