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Method and device for decreasing ADC (analog to digital converter) sampling rate in digital pre-distortion

A digital pre-distortion and sampling rate technology, applied in improving amplifiers to reduce nonlinear distortion, power amplifiers, high-frequency amplifiers, etc., can solve the problem of high precision and high-speed ADC prices, and achieve the effect of reducing demand

Active Publication Date: 2015-01-28
优镓科技(北京)有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For a broadband transmitter system, if the signal bandwidth is 40M, the sampling rate of the ADC needs to be over 200M to collect the distortion in the entire bandwidth, and the price of high-precision high-speed ADC is relatively high. A disadvantage of distortion applications

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  • Method and device for decreasing ADC (analog to digital converter) sampling rate in digital pre-distortion

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Embodiment Construction

[0036] Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary and are intended to explain the present invention and should not be construed as limiting the present invention.

[0037] The present invention provides a method and device for reducing ADC sampling rate in digital pre-distortion. The method and device are aimed at digital pre-distortion (DPD, Digital Pre-Distortion) of radio frequency power amplifiers used in communication, broadcasting, microwave transmission and other systems. The design of the invention can greatly reduce the requirement of high-speed ADC for equipment.

[0038] The core idea of ​​the present invention is that the forward model does not have obvious requirements on the ou...

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Abstract

The invention provides a method and a device for decreasing ADC (analog to digital converter) sampling rate in digital pre-distortion. The method includes the steps of subjecting an input signal of a power amplifier and an output signal thereof to time alignment by means of shifting input; estimating forward model parameters of the power amplifier through a forward model; according to the estimated forward model parameters, estimating a full-sampling-rate output signal of the power amplifier; according to the estimated output signal of the power amplifier and an actual input signal of the power amplifier, establishing an adverse model and estimating parameters of a pre-distorter; copying pre-distortion parameters to the pre-distorter to perform digital pre-distortion. The method and the device have the advantage that the demands of equipment on a high-speed ADC are greatly lowered.

Description

technical field [0001] The invention relates to the technical field of digital predistortion processing, in particular to a method and device for reducing the ADC sampling rate in digital predistortion. Background technique [0002] With the development of communication technology, broadband signals and complex modulation methods are applied. For example: QPSKQuadrature Phase Shift Keying, Quadrature Phase Shift Keying), 16QAM (Quadrature Amplitude Modulation, Quadrature Amplitude Modulation), 64QAM, etc. Complex modulation methods will bring error vector magnitude (EVM, Error Vector Magnitude) and adjacent The deterioration of the channel power ratio (ACPR), the pre-distortion technology is also applied, and the current research is more on the digital pre-distortion technology. [0003] figure 1 An existing indirect learning based digital predistortion system is shown. From figure 1 It can be seen that the existing digital predistortion system based on indirect learning...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03F3/20H03F3/189H03F1/32
Inventor 王宗浩陈文华苏公喆
Owner 优镓科技(北京)有限公司