An output time keeping circuit and method

Abstract

The present invention provides an output time keeping circuit and method, wherein the device includes: a voltage comparison unit, used to compare the working voltage with a preset reference voltage to obtain at least two comparison result signals; an enabling unit, It is used to generate at least two enabling signals according to the at least two comparison result signals; the clock driving unit is used to receive the reference clock; The controller chain is used to adjust the reference clock to at least two working clocks of corresponding sizes. The present invention can maintain the delay of the working clock in a relatively stable range, thereby making the holding time of the output data relatively stable, facilitating the sampling of the output data, and not increasing the transmission delay of the output data.

Description

technical field [0001] The invention relates to the technical field of electronic circuits, in particular to an output time keeping circuit and an output time keeping method. Background technique [0002] The output data hold time is an important parameter to measure the output design. Using the output data circuit designed by the existing technology, the delay of the circuit is greatly affected by the change of the working voltage, and with the change of the working voltage, the working speed of the circuit will also increase. There are large-scale changes, and changes in working speed will expand the range of output data retention time windows. Once the range of output data retention time windows is too large, it will increase the difficulty of sampling output data. Therefore, in order to facilitate the sampling of the output data, it is necessary to maintain the holding time of the output data within a relatively small range, and at the same time, the data output speed wi...

AI Technical Summary

Problems solved by technology

[0002] The output data hold time is an important parameter to measure the output design. Using the output data circuit designed by the existing technology, the delay of the circuit is greatly affected by the change of the working voltage, and with the change of the working voltage, the working speed of the circuit will also increase. There are large-scale changes, and the change of working speed will expand the change range of the output data retention time window. Once the change range of the output data retention time window is too large, it will increase the difficulty of sampling the output data.

Therefore, in order to facilitate the sampling of output data, it is necessary to maintain the hold time of output data within a small range, and at the same time, it will not affect the data output speed, thereby increasing the output data transmission delay in disguise.

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