Data storage scheduling method and device for multiple types of storage

Abstract

The embodiment of the invention discloses a data storage scheduling method and device for multiple memories, which can ensure the access load balance among the memories, and further improve the programming speed, erasing times and memory bandwidth saving. The embodiment of the present invention includes: obtaining characteristic parameters of various types of memory used to indicate data partitioning, the characteristic parameters include read and write delay characteristics of various types of memory, the size of the data set moved to the data read and write buffer, and access to various types of memory The number of misses of each data set in the data read-write buffer, where the data read-write buffer is a temporary cache module for the data set moved out of the storage array in each memory; according to the characteristic parameters, store in each memory The data sets of the data sets are prioritized separately; the data sets of the same priority are triggered to be stored in the memory corresponding to the level and the data priority.

Description

technical field [0001] The present invention relates to the field of communication technology, in particular to a data storage scheduling method and device for multiple types of memories. Background technique [0002] At present, dynamic random access memory (DRAM, Dynamic Random Access Memory) is difficult to miniaturize after the 20nm process, the capacity cannot be increased, and the refresh power consumption is large, causing serious waste. The new type of non-volatile memory (NVM, Non-Volatile Memory), such as phase change memory (PCM, Phase change memory) has the advantages of strong miniaturization ability, large capacity, and low power consumption, but the read and write delay of NVM is lower than that of DRAM. Much larger, NVM has a limited number of erases and writes. From this was born the concept of hybrid storage. [0003] In the existing mixed storage solution of PCM and DRAM, DRAM is used as a buffer for accessing PCM, and all data read or written to PCM is ...

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Problems solved by technology

[0004] However, in this solution, moving data only considers the increase in the cache usage of the data itself. However, due to the unbalanced memory request load between DRAM and NVM, the improvement in writing speed, erasing times, and saving memory bandwidth has not been optimized.

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