Storage scheduling method and device for data among multiple kinds of storages

Abstract

A method and device for data storage scheduling among multiple memories, ensuring access load balancing between memories, and further improving on programming speed, number of rewrite times, and memory bandwidth saving; the method comprising: acquiring characteristic parameters of each type of memory used for specifying data partitioning, the characteristic parameters comprising the read / write delay characteristic of each type of memory, the size of a data set moved to a data read-write buffer area, and the number of times each accessed data set in each type of memory is missed in the data read-write buffer area, the data read-write buffer area being a module in each memory for temporarily caching the data set moved out of a storage array; according to the characteristic parameters, respectively prioritizing the data sets stored in each memory; and triggering the storage of the data sets having the same priority into the memory corresponding to the data priority.

Description

technical field [0001] The present invention relates to the field of communication technology, in particular to a data storage scheduling method and device for multiple types of memories. Background technique [0002] At present, dynamic random access memory (DRAM, Dynamic Random Access Memory) is difficult to miniaturize after the 20nm process, the capacity cannot be increased, and the refresh power consumption is large, causing serious waste. The new type of non-volatile memory (NVM, Non-Volatile Memory), such as phase change memory (PCM, Phase change memory) has the advantages of strong miniaturization ability, large capacity, and low power consumption, but the read and write delay of NVM is lower than that of DRAM. Much larger, NVM has a limited number of erases and writes. From this was born the concept of hybrid storage. [0003] In the existing mixed storage solution of PCM and DRAM, DRAM is used as a buffer for accessing PCM, and all data read or written to PCM is ...

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Problems solved by technology

[0004] However, in this solution, moving data only considers the increase in the cache usage of the data itself. However, due to the unbalanced memory request load between DRAM and NVM, the improvement in writing speed, erasing times, and saving memory bandwidth has not been optimized.

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