Low-power-consumption logic circuit

Abstract

The embodiment of the invention relates to a low-power-consumption logic circuit. The low-power-consumption logic circuit comprises a current limiting circuit, a first transistor set and a second transistor set. The current limiting circuit is connected to an output end. The source electrode of the first transistor set is connected to a power supply end, the grid electrode of the first transistor set is connected to an input end, and the drain electrode of the first transistor set is connected to the current limiting circuit. The source electrode of the second transistor set is connected to a grounding end, the grid electrode of the second transistor set is connected to the input end, and the drain electrode of the second transistor set is connected to the current limiting circuit. When the first transistor set is switched on, a first current flows through the current limiting circuit to the second transistor set and is limited by the current limiting circuit to have the current value no larger than a preset threshold value, or when the second transistor set is switched on, a second current flows through the current limiting circuit to the first transistor set and is limited by the current limiting circuit to have the current value no larger than a preset threshold value. Thus, the problem that because an existing logic circuit consumes a large dynamic current when signals of the input end change, a system needs to be charged frequently or a battery of the system needs to be replaced frequently is can be solved.

Description

technical field [0001] The invention relates to the field of logic circuits, in particular to a logic circuit with low power consumption. Background technique [0002] With the development of the Internet of Things technology, people gradually have a demand for battery-powered systems that do not need to be charged for a long time and do not need to be replaced frequently, which requires that the power consumption of the system is relatively low (for example, according to the standard of down to the microampere level). [0003] The digital circuit in the existing system consumes a large dynamic current power consumption when it is flipped, which leads to a relatively large average power consumption of the system. Such as figure 1 shown in the circuit diagram of the existing logic circuit, as figure 1 shown, including a PMOS transistor and an NMOS transistor. Wherein, the source of the PMOS transistor is connected to the power supply VDD, and the source of the NMOS transi...

AI Technical Summary

Problems solved by technology

[0005] The embodiment of the present invention provides a low-power logic circuit, which can solve the problem that the existing logic circuit consumes a large amount o

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