Graded sending dispatching circuit structure based on AFDX network switch chip

Abstract

The invention provides a graded sending dispatching circuit structure based on an AFDX network switch chip. The sending dispatching structure comprises a host interface, a switch channel switch logic, a switch port queue control module, a host queue control module, an end system queue control module, a catching queue control module and a sending dispatching arbiter. The graded sending dispatching circuit structure has the advantages that the size of buffer regions with high and low priorities of the switch port queue can be configured, meanwhile, a host interface and end system data request is dispatched, and the sending dispatching request of the switch port is fairly dispatched under the condition of ensuring high priority of the end system request.

Description

technical field [0001] The invention belongs to integrated circuit design technology, and relates to a hierarchical transmission scheduling circuit and scheduling method for AFDX switches. Background technique [0002] AFDX network is the transmission network technology of the new generation avionics system, which has the characteristics of high speed, determinism and stability. [0003] As an important part of the AFDX network, the AFDX switch is designed in the form of store-and-forward according to the requirements of the AFDX standard, and limits and requires the buffer data size and sending priority of each port. Since the store-and-forward mode is adopted, it is necessary to save and schedule the exchange information in the exchange process, so as to complete the reading and sending of the exchange data in the storage area. The traditional method adopts the form of a linked list to realize the management of the queue information of the relevant switching ports, which ...

AI Technical Summary

Problems solved by technology

[0004] In order to solve the existing technical problems that are difficult to implement in the form of linked lists, the present invention provides a hierarchical transmission scheduling circuit and scheduling method for AFDX switches, which can realize various types of information on switching ports, host ports, end systems, and capture ports. The in-and-out team management and hierarchical scheduling are realized by hardware, which improves the operating efficiency and can meet a series of technical requirements of switches based on the AFDX standard for switching port buffer depth, high priority for end system scheduling, and fair scheduling of switching ports.

Images