Rapidly-adaptive all-digital phase-locked loop and design method thereof

Abstract

The invention discloses a rapidly-adaptive all-digital phase-locked loop and a design method thereof. The rapidly-adaptive all-digital phase-locked loop comprises a digital phase discriminator, a digital filter, a numerically-controlled oscillator and an adaptive controller, wherein the digital phase discriminator is used for subjecting an input signal ui and an output signal uo fed back to the input end of the phase-locked loop to phase discrimination and transmitting a phase error signal e reflecting the input signal and the output signal to the digital filter and the adaptive controller, the adaptive controller is used for generating a corresponding control signal c according to input signal frequency change and the phase error signal and transmitting the control signal c to the digital filter, the digital filter is capable of changing intrinsic parameters of the phase error signal and the control signal after receiving the phase error signal and the control signal, and generates a control signal N, and the numerically-controlled oscillator is used for adjusting frequency and phase of the output signal of the phase-locked loop, so that the all-digital phase-locked loop can be locked rapidly.

Description

technical field [0001] The invention belongs to the field of electronic technology, and relates to a fast adaptive all-digital phase-locked loop and a design method thereof. Background technique [0002] In recent years, scholars at home and abroad have conducted extensive research on all-digital phase-locked loops for various purposes, and many novel phase-locked loop structures have emerged as the times require. At the same time, the on-chip phase-locked loop with high performance and versatility has been deeply researched. Among them, the more representative research work mainly includes: Shan Changhong and others proposed a fast all-digital phase-locked loop with automatic modulus control, in which the modulus of the digital loop filter can be automatically adjusted according to the size of the phase error. Adjustment, to achieve real-time control of the loop bandwidth, effectively solve the contradiction between the capture speed and anti-noise performance; After a de...

AI Technical Summary

Problems solved by technology

Expanding the loop bandwidth can expand the capture range, speed up the phase-locking speed, and improve the dynamic performance of the phase-locked loop, but it will increase the phase jitter, reduce the anti-interference performance of the system, and cause the stability of the system to deteriorate; on the contrary, narrowing the loop bandwidth, It can reduce phase jitter, improve the anti-interference performance of the system, and enhance the stability of the system, but it narrows the capture range of the phase-locked loop and slows down the phase-locking speed

Using PID or PI control method alone can improve the dynamic performance or static performance of the system, but because it cannot implement dynamic control, once the design is completed, its control parameters are fixed, and only a compromise solution can be adopted in the design

Therefore, the contradiction between improving the dynamic performance of the phase-locked loop and enhancing the steady-state performance cannot be completely resolved

[0004] With the development of CMOS technology and the continuous improvement of system integration, it has become a popular trend to develop on-chip phase-locked loops with high performance and high versatility. However, the currently used all-digital phase-locked loops cannot Solve the contradiction between phase-locking speed, anti-noise ability and phase-locking range, which cannot meet the requirements of actual engineering systems

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