57results about How to "Optimize circuit structure" patented technology

An integrated circuit back end capacitor structure includes a first dielectric layer on a substrate, a thin film bottom plate on the first dielectric layer, and a second dielectric layer on the first dielectric layer and the bottom plate, and a thin film top plate disposed on the second dielectric layer. The thin film top plate and bottom plate are composed of thin film resistive layers, such as sichrome, which also are utilized to form back end thin film resistors having various properties. Interconnect conductors of a metallization layer contact the top and bottom plates through corresponding vias.

The present invention discloses a non-volatile ferroelectric cell array circuit using PNPN diode characteristics. The non-volatile ferroelectric cell array circuit includes a plurality of top sub cell arrays, a plurality of bottom sub cell arrays, a main bit line sense amp and a word line driving unit. Especially, the top and bottom sub cell arrays have a double bit line sensing structure for inducing a sensing voltage of a main bit line by controlling an amount of a current supplied from a power voltage to the main bit line according to a sensing voltage of a sub bit line receiving a cell data. Each of the sub cell arrays includes a ferroelectric capacitor, and a serial PN diode switch having a PNPN diode and a PN diode, to decrease a cell size and improve operational characteristics of the circuit.

An image data processing circuit including: an input section for inputting image data; a plurality of compressing sections which are capable of compressing the input image data solely or in parallel; a plurality of decompressing sections which are capable of decompressing the compressed image data solely or in parallel; an output section for outputting the decompressed image data; a transferring section for transferring image data between a memory and of the input section, the compressing sections, the decompressing sections and the output section individually; and a transfer controlling section for selecting a mode from a parallel input / output mode, a parallel input mode and a parallel output mode.

The present invention discloses a non-volatile ferroelectric cell array block having a hierarchy transfer sensing architecture. The cell array block of the invention includes a plurality of sub cell arrays, each with a hierarchy bit line architecture; a plurality of sub bit line sense amplifiers for amplifying a voltage of a sub bit line; main bit line sense amplifier for amplifying a voltage of a main bit line; and a word / plate driver for selectively activating the word line and the plate line in the sub cell array. The cell array block of the invention can be advantageously used for performing more stable read and write operations on a data even with a small sized cell, by having a sub bit line capacitance independent of the main bit line.

A manufacturing method of an organic light emitting diode (OLED) display includes: supplying a circuit film on the pad area of the display panel and bonding a first end portion of the circuit film to the pad area; vertically standing and inserting the display panel in a bonding device; holding a portion of the circuit film including a second end portion to be horizontal by using a rotating device including a vacuum absorbing portion; supplying a flexible printed circuit (FPC) into a space under the second end portion of the circuit film, and attaching the flexible printed circuit to the second end portion of the circuit film; and operating the rotating device to move the second end portion to a vertical position, and separating the circuit film from the vacuum absorbing portion.

Disclosed is a method for protecting data information of an electronic device, comprising the following steps: 1) performing power-on detection on an electronic device of which production and installation are completed, detecting the stray capacitance of a signal line thereof, and recording same as a standard value of the signal line; 2) during a power-on operation, monitoring the stray capacitance of the signal line; 3) comparing the monitored capacitance value with the standard value, and entering step 4) when exceeding the set threshold value, otherwise entering step 2); and 4) erasing significant data in the electronic device. The method uses the manner of monitoring the stray capacitance to monitor the contact of outside foreign matter with the signal line, guarantees the security of data in the electronic device, and has the characteristics that the implementation process is simple and easy, safe and reliable, and the cost is low.

The present invention discloses a life-sustainable power supply system for a computer. The system comprises: a first rectifying circuit, wherein the first rectifying circuit is connected with an alternating current power source, and the output end of the first rectifying circuit is connected with a constant current stabilizing circuit; and a battery pack, wherein the contact end of the battery pack is connected with the output end of the first rectifying circuit. A positive electrode of each battery extends out of a first conductive slider; a negative electrode of each battery extends out of asecond conductive slider; each of the first conductive sliders is slidably provided with a first ring; each of the second conductive sliders is slidably provided with a second ring; the first ring and the second ring are concentrically arranged and synchronously rotated; the first ring is provided with a first plate, and the second ring is provided with a second plate; the first plate and the second plate are correspondingly spaced apart; the first conductive slider is in sliding conductive contact with the first plate; and the second conductive slider is in synchronous sliding conductive contact with the second plate. According to the technical scheme of the present invention, the technical problem that the computer with insufficient power supply is solved.

The invention relates to a high-voltage side driving circuit which comprises a bridge rectifier, a bootstrap capacitor, a signal generator and a latch circuit, wherein the bootstrap capacitor is coupled with a source electrode of a high-voltage side transistor; the bridge rectifier is coupled with the signal generator; the signal generator is provided with a first pulse output end and a second pulse output end, wherein the first pulse output end or the second pulse output end outputs a pulse signal after a time interval; and the latch circuit is provided with a setting end, a resetting end and an output end, wherein the setting end is coupled with the first pulse output end, the resetting end is coupled with the second pulse output end, and the output end is coupled with a gate electrode of the high-voltage side transistor.