Data prefetch for chip having parent core and scout core

Abstract

Embodiments relate to a method and computer program product for prefetching data on a chip having at least one scout core and a parent core. The method includes saving a prefetch code start address by the parent core. The prefetch code start address indicates where a prefetch code is stored. The prefetch code is specifically configured for monitoring the parent core based on a specific application being executed by the parent core. The method includes sending a broadcast interrupt signal by the parent core to the at least one scout core. The broadcast interrupt signal being sent based on the prefetch code start address being saved. The method includes monitoring the parent core by the prefetch code executed by at least one scout core. The scout core executes the prefetch code based on receiving the broadcast interrupt signal.

Description

technical field [0001] The present invention relates generally to multi-core chips having a mother core and a scout core, and more particularly to specifying a prefetch algorithm for a mother core in a multi-core chip. Background technique [0002] Multiple cores may be on a single chip. In one approach, a second core on the same chip as the parent core can be provided as a scout core. In a method of borrowing or utilizing a scout core, the scout core is used to prefetch data from a shared cache into a private cache of the parent core. This approach may be particularly useful in the event that the mother core encounters a cache miss. A cache miss occurs when the specified data line causes a search of the mother core's directory and the requested cache line does not exist. A typical way to get a cache line that misses is to initiate a fetch operation to a higher level cache. The scout core provides a mechanism for prefetching data needed by the parent core. [0003] It s...

AI Technical Summary

Problems solved by technology

[0003] It should be noted that different applications behave differently, with the result that a prefetching algorithm or method may not always be able to improve the latency of accessing the contents of the cache

In particular, if the mother core is executing several different applications, for example, the prefetch algorithm used to monitor the different applications may provide different latencies for accessing the contents of the cache based on the specific application being executed.

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