Frame header rapid synchronization system and method
A synchronization system and frame header technology, applied in the field of satellite data transmission data reception and processing, can solve the problem that the frame header synchronization method cannot meet the data processing speed requirements, etc., and achieve the effect of meeting the data processing speed requirements.
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specific Embodiment approach 1
[0043] Specific implementation mode one: the following combination figure 1 and figure 2 Describe this embodiment, the frame header fast synchronization system described in this embodiment includes:
[0044] An input buffer module 1 for buffering unsynchronized Nbit parallel frame data and outputting Nbit parallel frame data under the control of the control module 10; N is an integer multiple of 8, ranging from 32 to 512;
[0045] An input selection module 2 for selecting and outputting the Nbit parallel frame data received in the input buffer module 1 and the Nbit pre-synchronized buffer data received in the pre-synchronized buffer module 16 under the control of the control module 10; the value of L is 8 Integer multiples, ranging from 8 to 64; L is less than N;
[0046] A first-level cache module 3 for performing a first-level cache of the Nbit data selected and output by the input selection module 2;
[0047] A secondary cache module 4 for receiving the Nbit data output b...
specific Embodiment approach 2
[0060] Specific embodiment two: this embodiment is described further to embodiment one, and the specific process that control module 10 determines to retrieve frame header is: judge whether there is frame header in the Nbit data that frame header compares result module 9 output, if compare A 1 occurs in the Nbit data output by the frame header comparison result module 9 in the pair, then it is determined to be a frame header mark; if multiple 1s occur in the Nbit data output by the frame header comparison result module 9 in a comparison, Then select the lowest bit 1 and determine it as the frame header mark.
specific Embodiment approach 3
[0061] Specific implementation mode three: the following combination figure 1 and figure 2 Describe this embodiment, the frame header fast synchronization method described in this embodiment includes:
[0062] A step for buffering unsynchronized Nbit parallel frame data through the input buffer module 1, and outputting Nbit parallel frame data under the control of the control module 10; N is an integer multiple of 8, ranging from 32 to 512;
[0063] A step for selecting and outputting the Nbit parallel frame data received in the input buffer module 1 and the Nbit pre-synchronized buffer data received in the pre-synchronized buffer module 16 under the control of the control module 10 through the input selection module 2; the value of L is Integer multiples of 8, ranging from 8 to 64; L is less than N;
[0064] A step for performing a first-level cache of the Nbit data selected and output by the input selection module 2 through the first-level cache module 3;
[0065] A step...
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