Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

System and method for quick frame header synchronization

A synchronization system and frame header technology, which is applied in the field of satellite data transmission data receiving and processing, can solve the problem that the frame header synchronization method cannot meet the data processing speed requirements, and achieve the effect of meeting the data processing speed requirements

Active Publication Date: 2017-09-26
HARBIN INST OF TECH
View PDF5 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The purpose of the present invention is to solve the problem that the existing frame header synchronization method cannot meet the data processing speed requirements with the increase of satellite data code rate level, and provides a frame header fast synchronization system and method

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • System and method for quick frame header synchronization
  • System and method for quick frame header synchronization

Examples

Experimental program
Comparison scheme
Effect test

specific Embodiment approach 1

[0043] Specific implementation mode one: the following combination figure 1 and figure 2 Describe this embodiment, the frame header fast synchronization system described in this embodiment includes:

[0044]An input buffer module 1 for buffering unsynchronized N bit parallel frame data and outputting N bit parallel frame data under the control of the control module 10; N is an integer multiple of 8, ranging from 32 to 512;

[0045] An input selection module 2 for selecting and outputting the N bit parallel frame data received in the input buffer module 1 and the N bit pre-synchronized buffer data received in the pre-synchronized buffer module 16 under the control of the control module 10; the value of L is 8 Integer multiples of , ranging from 8 to 64; L is less than N;

[0046] A first-level cache module 3 for performing a first-level cache of the N bit data selected and output by the input selection module 2;

[0047] A secondary cache module 4 for receiving N bit data o...

specific Embodiment approach 2

[0060] Specific embodiment two: this embodiment is further described to embodiment one, and the specific process that control module 10 determines to retrieve frame header is: judge whether there is frame header in the N bit data that frame header comparison result module 9 outputs, if in one time If a 1 occurs in the N bit data output by the frame header comparison result module 9 in the comparison, then it is determined to be a frame header mark; 1, then select the lowest 1 and determine it as the frame header mark.

specific Embodiment approach 3

[0061] Specific implementation mode three: the following combination figure 1 and figure 2 Describe this embodiment, the frame header fast synchronization method described in this embodiment includes:

[0062] A step for buffering unsynchronized N bit parallel frame data through the input buffer module 1, and outputting N bit parallel frame data under the control of the control module 10; N is an integer multiple of 8, ranging from 32 to 512;

[0063] A step for selecting and outputting the N bit parallel frame data received in the input buffer module 1 and the N bit pre-synchronized buffer data received in the pre-synchronized buffer module 16 under the control of the control module 10 through the input selection module 2; The value is an integer multiple of 8, ranging from 8 to 64; L is less than N;

[0064] A step for performing a first-level cache of the N bit data selected and output by the input selection module 2 through the first-level cache module 3;

[0065] A st...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A frame header fast synchronization system and method belong to the technical field of satellite digital transmission data receiving and processing. The invention aims to solve the problem that the existing frame head synchronization method cannot meet the data processing speed requirement with the increase of the satellite transmission data code rate level. The system and method of the present invention can realize the processing and synchronization of high-speed data communication, perform serial-to-parallel conversion on the data received from the base equipment, and process the data with N bit width as the internal data bit width, thereby realizing Simultaneous processing of N bit data meets the data processing speed requirements of satellite data. The invention is used for fast synchronization of the frame head of satellite data transmission data.

Description

technical field [0001] The invention relates to a frame header fast synchronization system and method, and belongs to the technical field of satellite data transmission data receiving and processing. Background technique [0002] In the field of communication, frame header synchronization is the most important part of data processing, and it is the basis of subsequent data processing. At present, the format of satellite data transmission data mostly follows the AOS data format standard formulated by CCSDS. This standard requires data to be downloaded in units of data frames. The beginning of the data frame is marked by the agreed data frame header, and the data is downloaded to the ground station. Therefore, frame header synchronization is the first element of satellite data transmission data reception and processing. At present, as the data code rate climbs from the traditional Mbps level to Gbps level, the time left for frame header synchronization is getting shorter and ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H04J3/06H04L7/04
Inventor 王少军马宁姬耀崔新莹刘大同彭宇
Owner HARBIN INST OF TECH
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products