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Microelectronic package with wire bonding vias, method of making same, and reinforcement layer for microelectronic package

A wire bonding and bonding technology, which is applied in the fields of electrical solid-state devices, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as limited micro-contact configurations

Active Publication Date: 2018-06-01
INVENSAS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Also, configurations of microcontacts formed by conventional etching processes are limited

Method used

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  • Microelectronic package with wire bonding vias, method of making same, and reinforcement layer for microelectronic package
  • Microelectronic package with wire bonding vias, method of making same, and reinforcement layer for microelectronic package
  • Microelectronic package with wire bonding vias, method of making same, and reinforcement layer for microelectronic package

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Embodiment Construction

[0087] Turning now to the drawings, in which like reference numerals are used to indicate like features, in figure 1 Illustrated in is a microelectronic assembly 10 according to one embodiment of the present invention. figure 1 An example of this is a microelectronic assembly in the form of a packaged microelectronic element, such as a semiconductor chip assembly used in a computer or other electronic application.

[0088] figure 1 The microelectronic assembly 10 includes a substrate 12 having a first surface 14 and a second surface 16 . Substrate 12 is generally in the form of a substantially planar dielectric element. The dielectric element may be sheet-like and may be thin. In specific embodiments, the dielectric element may comprise one or more layers of organic dielectric materials or composite dielectric materials such as, but not limited to: polyimide, polytetrafluoroethylene ("PTFE"), epoxy Resin, epoxy glass, FR-4, BT resin, thermoplastic, or thermosetting plas...

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Abstract

Microelectronic components and methods of forming such microelectronic components are disclosed herein. The microelectronic component may include a plurality of conductive vias in the form of wire bonds 32 extending from a bonding surface 30 of substrate 12 , such as a surface of a conductive element at a surface of substrate 12 .

Description

[0001] Cross References to Related Applications [0002] This application is a continuation of U.S. Application Serial No. 13 / 757,673, filed February 1, 2013, and is a continuation of U.S. Application Serial No. 13 / 757,677, filed February 1, 2013, the disclosure of which is incorporated by reference into this article. technical field [0003] The subject matter of the present application relates to methods of encapsulating microelectronic components and associated circuitry, such as methods of making structures, for example, with A microelectronic package with a plurality of conductive vias (via) in the form of wire bonds extending from the surface of the microelectronic package. Background technique [0004] Microelectronic devices such as semiconductor chips often require numerous input and output connections to other electronic components. The input and output contacts of a semiconductor chip or other comparable device are generally arranged in a grid-like pattern (com...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/498H01L21/48
CPCH01L23/3128H01L23/49811H01L21/4853H01L21/565H01L25/105H01L2224/16145H01L2224/16225H01L2224/32145H01L2224/32225H01L2224/32245H01L2224/48091H01L2224/48145H01L2224/48227H01L2224/48247H01L2224/73265H01L2225/0651H01L2225/06517H01L2225/1023H01L2225/1052H01L2225/1058H01L2924/15311H01L2924/1815H01L2924/19107H01L2225/06513H01L2225/06558H01L2225/06506H01L2225/06565H01L2225/06562H01L2225/06568H01L2224/45144H01L2224/45147H01L2924/181H01L24/73H01L2224/45565H01L2224/45624H01L2224/45655H01L2224/45664H01L2924/00012H01L2924/00H01L2924/00014
Inventor P·达姆博格赵志军E·乔R·阿拉托瑞
Owner INVENSAS CORP