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SRAM-based DCT input/output data caching method suitable for HEVC standard

A technology for input/output and data caching, which is applied in digital video signal modification, electrical components, image communication, etc., and can solve the problems that the register-based caching method is no longer applicable

Active Publication Date: 2016-03-02
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Under the HEVC standard, the maximum size of the image processing block (LCU) has reached 64×64, which makes the traditional register-based caching method no longer applicable

Method used

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  • SRAM-based DCT input/output data caching method suitable for HEVC standard
  • SRAM-based DCT input/output data caching method suitable for HEVC standard
  • SRAM-based DCT input/output data caching method suitable for HEVC standard

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Embodiment Construction

[0022] According to formula (1), there are the following mapping methods:

[0023] Pixel row 0-0-0 is mapped to memory cell 0-0;

[0024] Pixel row 0-0-1 is mapped to storage unit 1-1;

[0025] Pixel row 0-0-2 is mapped to memory cell 2-2;

[0026] Pixel row 0-0-3 is mapped to storage unit 3-3;

[0027] Pixel row 0-0-4 is mapped to memory cells 0-4;

[0028] Pixel rows 0-0-5 are mapped to memory cells 1-5;

[0029] Pixel rows 0-0-6 are mapped to memory cells 2-6;

[0030] Pixel rows 0-0-7 are mapped to memory cells 3-7;

[0031] Pixel row 0-1-0 is mapped to memory cell 2-0;

[0032] Pixel row 0-1-1 is mapped to storage unit 3-1;

[0033] Pixel row 0-1-2 is mapped to memory cell 0-2;

[0034] Pixel rows 0-1-3 are mapped to memory cells 1-3;

[0035] Pixel rows 0-1-4 are mapped to memory cells 2-4;

[0036] Pixel rows 0-1-5 are mapped to memory cells 3-5;

[0037] Pixel rows 0-1-6 are mapped to memory cells 0-6;

[0038] Pixel rows 0-1-7 are mapped to memory cells 1-...

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Abstract

The invention belongs to the technical field of compressing, coding and decoding of high-definition digital videos, and in particular relates to an SRAM-based DCT input / output data caching method suitable for an HEVC standard. According to the invention, 4 SRAMs with the depth of 128 and the pixel width of 8 are used; an image processing block with the size of 64*64 is equally divided into 4 1 / 4 image processing blocks with the size of 32*32; the 1 / 4 image processing blocks with the size of 32*32 are equally divided into 16 1 / 64 processing blocks with the size of 8*8; the 1 / 64 processing blocks with the size of 8*8 are equally divided into 8 image processing lines with the size of 1*8; and then, a corresponding storage relationship between data processed by various image blocks and addresses of various storage units in the various SRAMs is established. By using the method disclosed by the invention, the 32-pixel throughput rate in each period can be always provided no matter the size of an access block is 4*4, 8*8, 16*16 or 32*32 and no matter an access format is output according to the line or output according to the block; and thus, the relatively high throughput rate is achieved with the relatively low hardware cost.

Description

technical field [0001] The invention belongs to the technical field of high-definition digital video compression encoding and decoding, and specifically relates to a method for buffering DCT input and output data in the HEVC standard. Background technique [0002] HEVC (High Efficiency Video Coding) is a next-generation video codec standard proposed by JCTVC, an organization jointly established by the International Telecommunications Organization (ITU) and the Motion Picture Experts Group (MPEG). The goal is to double the compression rate compared to the previous generation standard, namely the H.264 / AVC standard, on the premise of the same visual effect. [0003] The video encoder based on HEVC is mainly composed of the following modules: intra prediction, inter prediction, transformation, quantization, inverse quantization, inverse transformation, reconstruction, deblocking filter, adaptive sample point compensation, etc. Among them, the discrete cosine transform (DCT) is...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N19/433H04N19/625H04N19/122
Inventor 范益波黄磊磊刘淑君曾晓洋
Owner FUDAN UNIV