Flying scoreboard processing method supporting out-order issue of simultaneous multithreading instructions

A processing method and a scoreboard technology, applied in the field of multi-thread processing, can solve the problem that Fi cannot release and reallocate the instruction n+i, etc., and achieve the effect of improving the energy consumption ratio and high launch efficiency.

Active Publication Date: 2016-04-27
上海高性能集成电路设计中心
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  • Summary
  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

At this time, the flying scoreboard processing method in the above-mentioned patent is no longer applicable. The reason is that when the instructions from different threads are interleaved, the order in which the instructions are submitted is different from the order in which the instruction registers are renamed. When the flight scoreboard number Fi is set, and the subsequent nth effective instruction n+i of the target register allows register renaming, the instruction i may not be executed yet, and the corresponding flight scoreboard number Fi is still meaningful, and Fi cannot be released and reassigned. For command n+i use

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  • Flying scoreboard processing method supporting out-order issue of simultaneous multithreading instructions

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[0042] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these examples are only used to illustrate the present invention and not to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms also fall within the scope defined by the appended claims of the present application.

[0043] The number of flight scoreboards set by the present invention is still equal to the number of free physical registers, assuming that the number is n. Initially, the flight scoreboard number is bound to all the free physical register numbers one by one in any order. When register renaming, a free physical register number (Pdc) is allocated to the target register (Rd) of an instruction, and a flight score card number (Fdci...

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Abstract

The present invention relates to a flying scoreboard processing method supporting out-order issue of simultaneous multithreading instructions. According to the method, flying scoreboards having the same number with idle physical registers are arranged, and the flying scoreboard number is bound with the idle physical register number. When the instruction is used for renaming the registers, the flying scoreboard number and the bounded idle physical register number are assigned to a target register of the instruction together; when the instruction is submitted, the currently assigned flying scoreboard number is unbound from the currently assigned physical register number, and the flying scoreboard number is rebound with the idle physical register number newly released by the instruction; and when the instruction is rolled back, the currently assigned flying scoreboard number and the currently assigned physical register number are recycled together, and the last assigned flying scoreboard number and the last assigned physical register number in the target register are recovered. The out-order issue problem of the instructions under the condition that multiple threads are simultaneously executed and share the same physical register is solved.

Description

technical field [0001] The invention relates to the technical field of multi-thread processing, in particular to a flight scoreboard processing method which supports out-of-order transmission of simultaneous multi-thread instructions. Background technique [0002] Instructions in the same thread are coherent by accessing the same logical register. The two instructions before and after write to the same logical register, indicating that there is a write-after-write (WAW) correlation between the two instructions; the former instruction reads a logical register, and the latter instruction writes the same logical register, indicating that there is a relationship between the two instructions. There is a read-after-write (WAR) correlation; the previous instruction writes a logical register, and the latter instruction reads the same logical register, indicating that there is a read-after-write (RAW) correlation between the two instructions. In order to improve the parallelism of i...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38G06F9/30
CPCG06F9/30094G06F9/3836G06F9/3838
Inventor 尹飞胡向东李俊
Owner 上海高性能集成电路设计中心
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