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System power failure protection realizing method for NAND FLASH

A technology of power failure protection and implementation method, which is applied in the protection of storage content to prevent loss, the generation of response errors, and the processing of electrical digital data, which can solve the problems of high hardware design cost and complexity

Active Publication Date: 2016-05-18
BEIJING MXTRONICS CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The technical problem to be solved by the present invention is: to overcome the deficiencies of the prior art, to provide a system power-down protection implementation method for NANDFLASH, to ensure the integrity of the system key data when the system is powered off, and to overcome the problems in the traditional technology. Disadvantages of high hardware design cost and complexity

Method used

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  • System power failure protection realizing method for NAND FLASH
  • System power failure protection realizing method for NAND FLASH
  • System power failure protection realizing method for NAND FLASH

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Embodiment Construction

[0062] A method for implementing system power-down protection for NANDFLASH, capable of saving system state information in real time, comprising the following steps:

[0063] 1. Map and manage all blocks in NANDFLASH through the first-level table, second-level table and third-level table;

[0064] 2. Power on the system, load the first-level meter, second-level meter and third-level meter, and restore the working state of the system;

[0065] 3. According to the data in the table, judge whether abnormal power failure occurs during the data update process.

[0066] 4. When the information stored in NAND Flash changes, update the first-level table, second-level table and third-level table;

[0067] Specifically, such as figure 1 As shown, step one is:

[0068] All the blocks in NANDFLASH are mapped and managed through the three-level table. NANDFLASH includes the first-level table area, the first-level table backup area, the second-level table area, the second-level table bac...

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Abstract

The invention discloses a system power failure protection realizing method for a NAND FLASH. The method comprises following steps: 1, carrying out mapping management to all blocks in the NAND FLASH through a first level stable, a second level table and a third level table; 2, electrifying a system, loading the first level stable, the second level table and the third level table, recovering the system to a working state; 3, judging whether an abnormal power failure is generated in a data updating process according to the data in the tables; and 4, when the information stored in the NAND FLASH changes, updating the first level stable, the second level table and the third level table. According to the method of the invention, after the new first level stable, the new second level table or the new third level table is written successfully, the original first level stable, the original new second level table or the original new third level table is erased; the tables are located in a searchable address range; therefore, after the system is electrified again after the power failure, the system stores the data in the tables completely; and the system state can be recovered according to the data in the tables.

Description

technical field [0001] The invention relates to the field of data storage, in particular to a NANDFLASH-based power-down protection method for a data storage system. Background technique [0002] The structure of NAND FLASH chip is generally divided into two levels: block and page. Block is the basic unit inside NANDFLASH. Due to the characteristics of NANDFLASH's own structure, there are often bad blocks in the chip, resulting in discontinuous physical addresses. In order to effectively use the storage space inside NANDFLASH, storage devices based on NANDFLASH generally use the FTL (FlashTranslationLayer) algorithm. The FTL algorithm achieves the management of bad blocks in the system through the mapping of logical addresses and physical addresses. A large amount of address mapping information inside the FTL is the basis for the normal operation of the entire system. When the system is unexpectedly powered off, if the address mapping information is being updated inside t...

Claims

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Application Information

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IPC IPC(8): G06F11/14G06F12/16
CPCG06F11/1448G06F12/16
Inventor 张志永宗宇谢俊玲谷羽穆雅莉李广才赵微刘银萍
Owner BEIJING MXTRONICS CORP
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