Device and method for realizing 65536 point FFT on basis of FPGA
A complex number addition and complex multiplication technology is applied in the field of devices that implement 65536-point FFT based on FPGA, which can solve problems such as slow FFT processing and operation speed, and achieve the effect of eliminating data input and output bottlenecks, fast processing speed, and reducing the use of RAM resources.
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[0047] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
[0048] The technical solution of the present invention adopts the radix-16 butterfly operation module as the data processing unit, so the FFT of 65536 point data needs four stages of operations, and each stage performs 4096 times of butterfly operations. After the data is serially input, it is first stored in the RAM storage module, and then a set of 16-point data is read each time according to a certain rule, and the 16-way parallel butterfly operation is perf...
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