A data processing apparatus and method for performing segmented operations

Abstract

A data processing apparatus and method are provided for performing segmented operations. The data processing apparatus comprises a vector register store for storing vector operands, and vector processing circuitry providing N lanes of parallel processing, and arranged to perform a segmented operation on up to N data elements provided by a specified vector operand, each data element being allocated to one of the N lanes. The up to N data elements forms a plurality of segments, and performance of the segmented operation comprises performing a separate operation on the data elements of each segment, the separate operation involving interaction between the lanes containing the data elements of the associated segment. Predicate generation circuitry is responsive to a compute descriptor instruction specifying an input vector operand comprising a plurality of segment descriptors, to generate per lane predicate information used by the vector processing circuitry when performing the segmented operation to maintain a boundary between each of the plurality of segments. As a result, interaction between lanes containing data elements from different segments is prevented. This allows very effective utilisation of the lanes of parallel processing within the vector processing circuitry to be achieved.

Description

technical field [0001] The present invention relates to a data processing device and method for performing segmentation operations. Background technique [0002] One known technique to increase the performance of data processing devices is to provide circuitry that supports the operation of vector operations. Vector operations are performed on at least one vector operand, where each vector operand includes a plurality of data elements. Performing a vector operation involves repeatedly applying an operation across multiple data elements within a vector operand. [0003] In a typical data processing system that supports the implementation of vector operations, a vector register file will be provided for storing vector operands. Thus, by way of example, each vector register within a vector register file may store a vector operand comprising a plurality of data elements. [0004] It is known that in some embodiments, a vector processing circuit (commonly referred to as a SIMD...

AI Technical Summary

Problems solved by technology

While GPUs are good at overlapping computations with memory accesses and thereby hiding latency, GPUs struggle when irregularities in data structures manifest themselves as computational load imbalances

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