Call gate expansion for 64 bit addressing

A 64-bit, gating technology, applied in the field of processors, can solve problems such as processor incompatibility

Inactive Publication Date: 2004-11-03
ADVANCED MICRO DEVICES INC
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, processors using the x86 architecture are not suitable for applications that require 64-bit addresses or operand sizes

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Call gate expansion for 64 bit addressing
  • Call gate expansion for 64 bit addressing
  • Call gate expansion for 64 bit addressing

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0023] now refer to figure 1 , in which a block diagram of an embodiment of a processor 10 is shown. The present invention is also applicable to other embodiments, or the present invention is accomplished with other embodiments. exist figure 1 In the embodiment, the processor 10 includes an instruction cache 12, an execution core 14, a data cache 16, an external interface unit 18, a memory management unit (MMU) 20, and a register file 22. In the illustrated embodiment, MMU 20 includes a set of segment registers 24, a first control register 26, a second control register 28, a local descriptor table register (LDTR) 30, a global descriptor (descriptor ) listing register (GDTR) 32. The instruction cache memory 12 is coupled to the external interface unit 18 , the execution core 14 , and the MMU 20 . The execution core 14 is further coupled to the MMU 20 , the register file 22 , and the data cache 16 . The data cache memory 16 is further coupled to the MMU 20 and the external ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

A processor supports a first processing mode in which the address size is greater than 32 bits. The address size may be nominally indicated as 64 bits, although various embodiments of the processor may implement any address size which exceeds 32 bits, up to and including 64 bits, in the first processing mode. The first processing mode may be established by placing an enable indication in a control register into an enabled state and by setting a first operating mode indication and a second operating mode indication in a segment descriptor to predefined states. Other combinations of the first operating mode indication and the second operating mode indication may be used to provide compatibility modes for 32 bit and 16 bit processing compatible with the x86 processor architecture (with the enable indication remaining in the enabled state). To call code operating in the first processing mode from the 32 bit or 16 bit code, a call gate descriptor is defined which occupies two entries in a segment descriptor table. By occupying two entries, each of which may otherwise store a segment descriptor, the call gate descriptor may include enough space to store an address in excess of 32 bits. Thus, a calling code segment may reference a call gate descriptor, which may reference the target code semgent and may provide an address within the address space of the target code segment, even if the address exceeds the address size in the calling code segment.

Description

technical field [0001] The invention relates to the field of processors, in particular to address and operand lengths in the processor. Background technique [0002] The x86 architecture (known as the IA-32 architecture) has been widely accepted in the market and has been a fairly successful product. Therefore, designing a processor using the x86 architecture has considerable advantages. The advantage of this type of processor is that it can write large-capacity software into the x86 architecture (considering that this processor can execute the software, and therefore the computer system using this processor is quite popular in the market because it has a large number of available software). [0003] As computer systems continue to develop, it is necessary to go one step further and use 64-bit address lengths (sometimes referred to as operand lengths). A larger address length allows the program to have a larger memory footprint (memory capacity occupied by instructions in...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/34G06F9/318G06F9/32G06F9/355
CPCG06F9/34G06F9/322G06F9/30185G06F9/342G06F9/30189G06F9/32
Inventor 凯文·J·马克格瑞斯
Owner ADVANCED MICRO DEVICES INC
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap