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A fft floating-point optimization method based on instruction-level parallel ilp and data-level parallel dlp

A floating-point optimization and data-level technology, applied in the direction of concurrent instruction execution, electrical digital data processing, special data processing applications, etc., can solve the problems of complex hardware platforms, fast Fourier transform research has not been developed, etc., to achieve efficient deployment , reduce the running clock overhead, and avoid the effect of clock overhead

Active Publication Date: 2018-10-23
UNIV OF SCI & TECH OF CHINA
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Problems solved by technology

[0004] Due to the complexity of the hardware platform for the combination of ILP and DLP technology, research on fast Fourier transform based on it has not been carried out.

Method used

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  • A fft floating-point optimization method based on instruction-level parallel ilp and data-level parallel dlp
  • A fft floating-point optimization method based on instruction-level parallel ilp and data-level parallel dlp
  • A fft floating-point optimization method based on instruction-level parallel ilp and data-level parallel dlp

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Embodiment Construction

[0037] The purpose of the present invention is to propose a floating-point version FFT optimization method suitable for instruction-level parallel ILP and data-level parallel DLP hardware platforms, in order to perform high-performance optimization on the hardware infrastructure provided by it. The following specific implementations only use the BWDSP104x platform as an example to discuss optimization methods, but the optimization techniques and methods in the present invention are not limited to the BWDSP104x platform. Any hardware platform of ILP and DLP is suitable for the optimization scheme of the present invention.

[0038] The BWDSP104x platform has 4 execution macros (x, y, z, t), each macro has 8 arithmetic logic units (ALU), 8 multipliers (MUL), 4 shifters (SHIFT), and 1 Supercomputer and a set of general-purpose register sets containing 128 registers. It has 11 stages of pipelines, and each instruction line can simultaneously parallel 16-word instructions.

[0039] In ...

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Abstract

The invention discloses an FFT floating point optimization method based on ILP and DLP. The method is characterized by including the following steps that firstly, the layer number of iteration is determined, and iteration is divided into three layers; secondly, by means of bit-reversed instruction and other operation, calculation of the in-degree layer is finished; thirdly, after calculation of the in-degree layer is finished, calculation, to be conducted, of the middle layer is classified, computation is conducted according to the odd layer condition and the even layer condition respectively, and the calculation result of the middle layer is obtained; fourthly, the calculation result of the middle layer is adjusted by simulating inter-macro transmission operation, and calculation of the out-degree layer is finished. By means of the method, instruction coherence and structure limitation problems existing in an algorithm can be solved, loading efficiency of computation parts is given full play of, and the average utilization rate of bottleneck resources is greatly increased.

Description

Technical field [0001] The invention belongs to the field of vector processing machines and digital signal processing, and specifically relates to a method for realizing efficient calculation of a floating-point version of FFT on a hardware platform based on ILP and DLP. Background technique [0002] Discrete Fourier Transform (DFT) is widely used in the field of modern signal processing systems, such as radar signal processing, SAR image processing, sonar calculation, video image algorithm, spectrum analysis, speech recognition, etc. Fourier transform calculation is a typical computationally intensive and memory-intensive application. For example, the computational complexity of the N-point DFT transform is O(N 2 ). In 1965 Cooley and Turkey proposed a fast Fourier transform (Fast Fourier Transform, FFT) calculation method, which can significantly reduce the amount of calculation, and the calculation complexity is reduced from the original O(N 2 ) Drops to O(Nlog 2 N). Signal p...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/14G06F7/57G06F9/38
CPCG06F7/57G06F9/3836G06F17/142
Inventor 顾乃杰任开新叶鸿周文博
Owner UNIV OF SCI & TECH OF CHINA
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