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FFT floating point optimization method based on ILP and DLP

A floating-point optimization and initialization technology, applied in complex mathematical operations, program control design, instruments, etc., can solve the problems of complex hardware platform, fast Fourier transform research has not been carried out, etc., to achieve efficient deployment and reduce running clock overhead , the effect of reducing the number of prefetches

Active Publication Date: 2016-11-09
UNIV OF SCI & TECH OF CHINA
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Problems solved by technology

[0004] Due to the complexity of the hardware platform for the combination of ILP and DLP technology, research on fast Fourier transform based on it has not been carried out.

Method used

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  • FFT floating point optimization method based on ILP and DLP
  • FFT floating point optimization method based on ILP and DLP
  • FFT floating point optimization method based on ILP and DLP

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Embodiment Construction

[0037] The purpose of the present invention is to propose a method for optimizing floating-point version FFT applicable to ILP and DLP hardware platforms, in order to perform high-performance optimization on the hardware infrastructure provided by it. The following specific embodiments only use the BWDSP104x platform as an example to discuss the optimization method, but the optimization technology and method in the present invention are not limited to the BWDSP104x platform. Any hardware platform of ILP and DLP is suitable for the optimization scheme of the present invention.

[0038] The BWDSP104x platform has 4 execution macros (x, y, z, t), each with 8 arithmetic logic units (ALU), 8 multipliers (MUL), 4 shifters (SHIFT), 1 A supercalculator and a general-purpose register bank of 128 registers. It has a total of 11-stage pipelines, and each instruction line can parallelize up to 16 word instructions at the same time.

[0039] In this embodiment, a kind of FFT floating-poi...

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Abstract

The invention discloses an FFT floating point optimization method based on ILP and DLP. The method is characterized by including the following steps that firstly, the layer number of iteration is determined, and iteration is divided into three layers; secondly, by means of bit-reversed instruction and other operation, calculation of the in-degree layer is finished; thirdly, after calculation of the in-degree layer is finished, calculation, to be conducted, of the middle layer is classified, computation is conducted according to the odd layer condition and the even layer condition respectively, and the calculation result of the middle layer is obtained; fourthly, the calculation result of the middle layer is adjusted by simulating inter-macro transmission operation, and calculation of the out-degree layer is finished. By means of the method, instruction coherence and structure limitation problems existing in an algorithm can be solved, loading efficiency of computation parts is given full play of, and the average utilization rate of bottleneck resources is greatly increased.

Description

technical field [0001] The invention belongs to the fields of vector processors and digital signal processing, and in particular relates to a method for realizing high-efficiency calculation of floating-point version FFT on a hardware platform based on ILP and DLP. Background technique [0002] Discrete Fourier Transform (DFT) is widely used in the field of modern signal processing systems, such as radar signal processing, SAR image processing, sonar calculation, video image algorithm, spectrum analysis, speech recognition, etc. Fourier transform calculation is a typical calculation-intensive and memory-intensive application. For example, the computational complexity of N-point DFT transform is O(N 2 ). In 1965, Cooley and Turkey proposed a fast Fourier transform (FFT) calculation method, which can significantly reduce the amount of calculation, and the calculation complexity is changed from the original O(N 2 ) down to O(Nlog 2 N). Signal processing applications usually...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/14G06F7/57G06F9/38
CPCG06F7/57G06F9/3836G06F17/142
Inventor 顾乃杰任开新叶鸿周文博
Owner UNIV OF SCI & TECH OF CHINA
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