Client signal mapping method and device, and client signal demapping method and device
A client signal and implementation method technology, applied in the field of communication, can solve the problems of complex mapping processing and high mapping processing complexity, and achieve the effect of reducing complexity
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Embodiment 1
[0028] see figure 2 , is a flowchart of a method for implementing client signal mapping provided in Embodiment 1 of the present invention, and may specifically include:
[0029] Step 210, divide part or all of the payload area of the optical channel payload unit or optical channel data branch unit into several sub-blocks, the size of the sub-blocks is N bytes, and N is greater than or equal to 1;
[0030] Step 230: Map the client signal to be transmitted into sub-blocks in the payload area at the granularity of N bytes.
[0031] It can be seen that in this embodiment, when the client signal is mapped, the block mapping of the client signal is performed with the block as the mapping granularity, which relatively reduces the complexity of the client signal mapping process and can adapt to the requirements of various rate services.
Embodiment 2
[0033] see first image 3 , is a schematic structural diagram of an OPUk payload area and an OPUk overhead area provided in Embodiment 2 of the present invention. In this implementation, the OPUk payload area is logically divided into M sub-blocks, and the size of each sub-block is N bytes. The size of the entire OPUk payload area is M*N bytes.
[0034] It can be understood that the size of the logically divided sub-blocks of the OPUk payload area can be arbitrary, that is, N can be any value that can be divisible by the number of bytes in the OPUk payload area.
[0035] Preferably, the OPUk payload area can be logically divided into sub-blocks according to the processing bit width of the processor, and the size of the logically divided sub-blocks is a submultiple of the processing bit width of the processor. For example, assuming that the processing bit width of the processor is 16*8=128 bits, the size of the logically divided sub-blocks can be 16 bytes, 8 bytes, 4 bytes, 2 ...
Embodiment 3
[0089] see first Figure 7 , is a schematic structural diagram of an OPUk payload area and an OPUk overhead area provided by Embodiment 3 of the present invention. In this implementation, the OPUk payload area is divided into: a block area and an adjustment area, wherein the block area is logically divided into M sub-areas block, the size of each sub-block is N bytes, and the size of the entire block area is M*N bytes.
[0090] It can be understood that the size of the sub-blocks logically divided by the OPUk block area can be arbitrary, that is, N can be any value that can be divisible by the number of bytes in the OPUk block area.
[0091] Preferably, the OPUk block area can be logically divided into blocks according to the processing bit width of the processor, and the size of the logically divided sub-blocks is a submultiple of the processing bit width of the processor. For example, assuming that the processing bit width of the processor is 16*8=128 bits, the logically di...
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