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Design method and system of cpu reference model for verification platform

A technology of reference model design and verification platform, applied in the field of CPU reference model design method and system

Active Publication Date: 2019-05-31
LILING FULLRIVER ELECTRONICS & TECH LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Based on this, it is necessary to provide a reasonable and effective verification platform CPU reference model design method and system for the current problem that there is no reasonable and effective verification platform CPU reference model design method

Method used

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  • Design method and system of cpu reference model for verification platform
  • Design method and system of cpu reference model for verification platform
  • Design method and system of cpu reference model for verification platform

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0022] like figure 1 As shown, a verification platform CPU reference model design method, including steps:

[0023] S100: classify the input / output interfaces of the equipment to be tested and the CPU, and distinguish between the CPU access interface and the internal logic interface.

[0024] There are multiple input / output interfaces connected between the device to be tested and the CPU. Here, these interfaces are classified to distinguish between the CPU access interface and the internal logic interface. Specifically, the signal interfaces interconnected with the CPU may be classified as CPU interfaces, and the remaining signal interfaces may be classified as internal logic interfaces.

[0025] S200: Monitor the access protocol and timing of the interface signals in the CPU access interface, and make statistics on the access operation behavior of the CPU to obtain monitoring statistical data.

[0026] In practical applications, an independent signal interface module IntfCp...

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Abstract

The invention provides a verification platform CPU (Central Processing Unit) reference model design method and system. The method comprises the steps of distinguishing a CPU access interface from an internal logic interface; monitoring an access protocol and a time sequence of an interface signal in the CPU access interface, and performing statistics on access operation of a CPU; updating monitoring statistical data to a preset independent verification environment variable; obtaining an initial verification platform CPU reference model by adopting a tree structure of UVM (Universal Verification Methodology); separating business generation and interface operation in the initial verification platform CPU reference model, and training the initial verification platform CPU reference model; and obtaining a universal verification platform CPU reference model. In the whole process, the initial verification platform CPU reference model is built based on the UVM, and the business generation and the interface operation in the initial verification platform CPU reference model are separated; and in addition, business and interface drivers can be reloaded through a code reloading mechanism embedded in the UVM.

Description

technical field [0001] The invention relates to the field of computer technology, in particular to a CPU (Central Processing Unit, central processing unit) reference model design method and system. Background technique [0002] For large-scale integrated circuit chips, the CPU interface is used as its training path and debugging path. During the verification process, the correctness of this path must be ensured, which is crucial to the success of the chip's final tape-out. [0003] For designs with the same CPU interface, the CPU reference model of the required verification platform is the same, while for CPUs with different interfaces, the operation types are similar, and only the specific operation behavior of the interface protocol is different. For designs with the same CPU interface, designing a common verification platform CPU reference model can reduce repetitive work in the process of building a verification environment. [0004] However, there is currently no reaso...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
CPCG06F30/398
Inventor 郭敏谢海春蒋汉柏廖北平
Owner LILING FULLRIVER ELECTRONICS & TECH LTD