Unlock instant, AI-driven research and patent intelligence for your innovation.

A kind of operation method of NAND gate array

An operation method and technology of NOT gate, applied in the field of operation of NAND gate array, which can solve the problems of large block size, inconvenience, and influence on the convenience of erasing action, etc.

Active Publication Date: 2019-11-05
MACRONIX INT CO LTD
View PDF8 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

It is inconvenient when the user only needs to change a small part of the code of the 3D NAND memory
With the increase of the density of the three-dimensional NAND memory, the number of stacked layers is also increasing, resulting in a larger block size, which affects the convenience of the erasing operation.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A kind of operation method of NAND gate array
  • A kind of operation method of NAND gate array
  • A kind of operation method of NAND gate array

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0080] Embodiments of the present invention are described in detail below with accompanying drawings. The present invention is not limited to the specific structures and methods disclosed in the embodiments. The invention may be implemented through other features, means of components or other embodiments. The preferred embodiments are only used to illustrate the content of the present invention, but not to limit the protection scope of the present invention. The scope of protection of the present invention is still based on the scope of claims. Those skilled in the art to which this invention pertains will understand that the described content includes its equivalent variations. Also, in different embodiments, similar elements are described with similar reference numerals.

[0081] figure 1 A simplified block diagram of an integrated circuit (integrated circuit) 100 is shown. The integrated circuit 100 includes a NAND flash memory array 110 . In some embodiments, the NAN...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The present invention discloses a NAND gate array operation method. The NAND gate array comprises a plurality of blocks comprising a plurality of memory units, wherein the one block of the memory unit comprises a plurality of strings, a channel side voltage can be applied on a plurality of channel lines, a control voltage can be applied on the selected subset of first string select switches, the terminals of second string select switches and the channel lines can form suspension connections, the tunneling of the partial memory units coupled to the unselected subset of the first string select switches can be inhibited, and a word line side erase voltage can be applied on the word line of the selected block so as to induce the tunneling of the partial memory units coupled to the word lines and the selected subset of the first string select switches.

Description

technical field [0001] The present invention relates to a high-density memory device, and in particular relates to an operation method of a NAND gate array, which is used for page erasing of a flash memory. Background technique [0002] As the critical dimensions of integrated circuit components shrink toward the limits of manufacturing technology, designers are seeking technologies that can achieve larger storage capacities at a lower cost per bit. Various technologies are pursuing a single chip containing multiple layers of memory cells. The operation of the three-dimensional NAND memory with multi-layer memory cells includes read, write and erase. [0003] In general, the erasing operation is usually performed on several blocks of memory cells and each block includes stacked layers of memory cells. However, the blocks of memory cells of high density NAND gates (high density NAND), especially high density 3D NAND gates (high density 3D NAND) are usually quite large. Thi...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/14
Inventor 张国彬
Owner MACRONIX INT CO LTD