A method for generating circuit structure of combinational logic unit reinforced by C unit
A technology of combinational logic and unit circuits, applied in the fields of electrical digital data processing, instruments, calculations, etc., can solve the problems of large circuit simulation time overhead and iteration cost, and achieve the effect of solving the large interactive time overhead
Active Publication Date: 2019-07-12
BEIJING INST OF CONTROL ENG
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Problems solved by technology
[0004] The technical problem solved by the present invention is: to overcome the deficiencies in the prior art, to provide a C unit reinforced combinational logic unit circuit structure generation method, and to solve the circuit simulation time overhead in the existing C unit reinforced combinational logic unit development technology Larger, need to continue to iterate and simulate the cost of a larger problem
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[0022] Aiming at the deficiencies in the prior art, the present invention proposes a method for generating a combined logic unit circuit structure reinforced by a C unit, which solves the problem that the circuit simulation time overhead in the existing development technology of a combined logic unit reinforced by a C unit is relatively large and needs to be continuously iterated And the cost that emulation brings is spent bigger problem, the present invention is described in further detail below in conjunction with accompanying drawing and specific combined logic unit design and verification implementation case:
[0023] Such as figure 1 Shown is a schematic flow chart of a method for generating a combined logic unit circuit structure reinforced by a C unit of the present invention. The method of the present invention includes unit type definition, reading a reference combinational logic unit library to select a corresponding combinational logic unit, adding a C unit circuit s...
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The invention discloses a method for generating a C unit reinforced combined logic unit circuit structure. The method comprises the following steps: firstly, selecting combined logic units to be reinforced, respectively adding C unit circuit structures so as to obtain reinforced combined logic units and logic description; secondly, generating testing vectors according to the logic description of the reinforced combined logic units, and traversing the width of MOSs in the C units so as to obtain an MOS width corresponding to the minimum time delay, and further obtain a reinforced combined logic unit circuit structure; finally, testing the obtained reinforced combined logic unit circuit structure by using the testing vectors, so as to obtain characterization parameters.
Description
technical field [0001] The invention relates to the technical field of circuit reinforcement, in particular to a method for generating a combined logic unit circuit structure for C unit reinforcement. Background technique [0002] With the advancement and development of integrated circuit technology, the size of a single MOS tube is getting smaller and smaller, making these integrated circuits susceptible to single event effects and cannot work normally. For chips used in aerospace products, anti-single event effect protection is very important , so it is an inevitable choice to carry out anti-single event design on the underlying unit library required for integrated circuit development, and to strengthen the design of the combinational logic unit in the unit library through the C unit circuit is currently a mainstream one with little performance impact and resource overhead. Less reinforcement. [0003] For the development of this kind of combinatorial logic unit based on ...
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IPC IPC(8): G06F17/50
CPCG06F30/331
Inventor 夏冰冰周凯高瑛珂吴军刘鸿瑾孙强刘波吴一帆
Owner BEIJING INST OF CONTROL ENG