10-bit slave address-based I2C bus verification method and system

Abstract

The invention discloses a 10-bit slave address-based I2C bus verification method. The method comprises the steps that a test excitation layer inputs test excitation to an input port of a host model; the host model creates a reading/writing process task to a to-be-tested I2C bus interface according to the test excitation; the to-be-tested I2C bus interface sends the reading/writing process task to a slave model through an SDA line; and the slave model makes a response to the reading/writing process task, the test excitation layer judges whether a response result of the slave model is correct or not, and if the response result is correct, the verification of the to-be-tested I2C bus interface is passed. A verification model is simple in structure; the verification method is concise, good in compatibility and suitable for different kernel buses; an I2C protocol is met; and functional points of reading/writing validity, boundary and the like of an I2C bus can be accurately verified. The invention furthermore discloses a 10-bit slave address-based I2C bus verification system, which has the abovementioned beneficial effects.

Description

technical field [0001] The invention relates to the field of bus interface technology, in particular to a method and system for verifying an I2C bus based on a 10-bit slave address. Background technique [0002] The I2C bus is a two-wire serial bus used to connect microcontrollers and peripheral devices. The master master initiates data transmission and generates a clock signal that allows transmission. Any addressed device is a slave machine Slave. Under standard conditions, 7-bit slave addresses are addressed, and 10-bit addresses are required as the system scale increases. However, the I2C bus verification model in the prior art often does not support slaves with 10-bit addresses, and the scope of application is narrow. Therefore, how to verify the I2C bus based on the 10-bit slave address is a technical problem to be solved by those skilled in the art. Contents of the invention [0003] The purpose of the present invention is to provide a method and system for I2C bus...

AI Technical Summary

Problems solved by technology

Under standard conditions, 7-bit slave addresses are addressed, and as the system scale increases, there is a demand for 10-bit addresses. However, the I2C bus verification model in the prior art often does not support slaves with 10-bit addresses, and the scope of application is narrow.

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