A design method for safe disconnection of pcie equipment

Abstract

The invention discloses a design method of PCIE equipment safe disconnection. The method comprises the steps of establishing PCIE link monitor and control and a protocol simulation unit to administer a real time monitor of the PCIE link monitor and control, when abnormal condition happens, the unit actively sending equipment response data labels to the mother board and CPU to inform the mother board actively that the data transmission is ceased, thus ensuring the completeness of the transmission mechanism, and segregating the abnormal equipment in the link to maintain the reliability of the system. In the actual use process of a PCIE equipment in a server system, the method achieves the safe protection amid disconnection of current PCIE equipment, and solves the problem of insufficient fault precaution, thus making sure that the server system can operate stably in high efficiency.

Description

technical field [0001] The invention relates to the technical field of computer communication, in particular to a design method for safe disconnection of PCIE equipment. Background technique [0002] In the current server system, the PCIE device is directly connected to the CPU of the main board to undertake the task of system data transmission. As the key external data channel of the server system, the reliability and stability of the data link affect the stable operation of the system. The current PCIE device is directly connected to the CPU of the motherboard, that is, the high-speed signal of the PCIE device is directly connected to the output end of the motherboard, which simplifies the interconnection of the system. As the PCIE device becomes more and more diversified, the operation of the PCIE device The stability is also different, affecting and restricting the stability of the system to varying degrees. [0003] In the current way of using PCIE devices, when the PC...

AI Technical Summary

Problems solved by technology

The current PCIE device is directly connected to the CPU of the motherboard, that is, the high-speed signal of the PCIE device is directly connected to the output end of the motherboard, which simplifies the interconnection of the system. As the PCIE device becomes more and more diversified, the operation of the PCIE device The stability is also different, affecting and restricting the stability of the system to varying degrees

[0003] In the current way of using PCIE devices, when the PCIE device in the system is pulled out and the bus transmission is suspended, the PCIE transmission link on the CPU side of the motherboard cannot receive the abnormality generated by the PCIE device, especially during the read and write operations. After the instruction is issued, if the PCIE transmission link is interrupted, the motherboard CPU will enter the infinite waiting mode, and then the system thread will be abnormal, causing the upper layer software to enter the loop overflow state. Therefore, the current processing response mechanism cannot realize the uninterrupted operation and maintenance of the system, that is, the current PCIE There are major disadvantages when the device is offline: first, the PCIE device is offline, and the CPU side of the motherboard is caught in a command response waiting cycle, which seriously affects the system operation; second, when there are many CRC check errors of the PCIE device, the system cannot predict possible abnormalities. Causes the mainboard CPU to repeatedly resend data, resulting in a decrease in system operating efficiency, and system reliability cannot be guaranteed

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