Long bit width time sequence accumulation multiplying unit

Abstract

The invention provides a long bit width time sequence accumulation multiplying unit, which comprises a clock, a data operation module and a carry register, wherein the data operation module carries out operation on data to finish various types of work; a full adder is arranged in the data operation module; the full adder segments products obtained by accumulation, and multiplicands into different intervals according to bit width, the bit widths of full adders in different intervals are subjected to addition calculation when the data operation module enters an accumulation working state, and carry information is stored in the carry register; and when a next clock edge comes, the product of the shifted multiplicand and carry data of a previous level is accumulated to generate a new product and carry data, the new product and carry data can be stored in the carry register, and circulation is carried out in the above way until data in a multiplier is completely shifted. The data bit width calculated by the multiplying unit can be infinitely increased so as to get rid of limitation, which is caused by the multiplication data bit width, for the maximum work clock frequency of the multiplying unit, and the multiplying unit can stably work under extremely high clock frequency.

Description

technical field [0001] The invention relates to the technical field of digital circuits, in particular to a long-bit-width sequential accumulation multiplier. Background technique [0002] As the basic unit in digital circuits, the digital multiplier has always played a pivotal role in data processing and timing control. Especially in digital signal processing, a large number of digital multipliers are used in digital low-pass, high-pass, and band-pass filters, and the speed of the multiplier often determines the speed of signal processing. In the CIS system, it is necessary to use a multiplier to calculate the exposure time. The system clock is fast, and the use of an ordinary multiplier often cannot meet the requirements. Therefore, it is necessary to optimize the existing timing accumulation multiplier so that the multiplier can adapt to the high-speed clock. demand. [0003] The commonly used timing accumulating multiplier shifts the multiplicand to the left by one bit...

AI Technical Summary

Problems solved by technology

But when the multiplicand data bit width is wide, the complexity of the full adder will increase exponentially, and its complex combinational logic limits the increase of the clock frequency, so that the multiplier can only run at low speed

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