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A dual-mode 8 memory access address calculation method

A technology of memory access address and calculation method, applied in the field of dual-mode 8 memory access address calculation, can solve problems such as prolonging operation completion time and conflict, and achieve the effect of shortening the execution cycle of imaginary matrix transposition

Active Publication Date: 2019-09-10
CHINA ELECTRONIC TECH GRP CORP NO 38 RES INST
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This kind of read and write sequence will generally lead to memory bank conflicts in multiple addresses during the read or write back process, prolonging the operation completion time

Method used

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  • A dual-mode 8 memory access address calculation method
  • A dual-mode 8 memory access address calculation method
  • A dual-mode 8 memory access address calculation method

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Embodiment Construction

[0062] A dual-mode 8 memory access address calculation method, the method comprises the steps of the following sequence:

[0063] (1) Select the corresponding dual-mode 8 access address calculation formula according to the type of the matrix. The real number matrix is ​​calculated using the single-word dual-mode 8 access address calculation formula, and the complex number matrix is ​​calculated using the double-word double-mode 8 access address calculation formula; dual-mode 8 memory access address refers to the access memory address generated based on two modulo 8 operations;

[0064] (2) Configure the corresponding base address and offset address according to the scale before matrix transposition;

[0065] (3) 4 or 8 effective addresses are generated after calculation by the dual-mode 8 memory access address calculation formula, and a set of data before matrix transposition is read with this address;

[0066] (4) Configure the corresponding base address and offset address a...

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Abstract

The invention relates to a dual-mode 8 access address calculation method. The method comprises the following steps: selecting a corresponding dual-mode 8 access address calculation formula according to the type of a matrix; configuring a corresponding base address and an offset address according to the scale of the matrix before transpose; generating 4 or 8 valid addresses by calculation, and reading a group of data of the matrix before transpose by the addresses; configuring a corresponding base address and an offset address according to the scale of the matrix after transpose; generating 4 or 8 valid addresses by calculation, and reading a group of data of the matrix after transpose; adding 1 to the base address to serve as a new base address; judging whether the transpose of the matrix is accomplished, if the judgment result is positive, executing the next step, and otherwise, returning to step 3; and terminating the matrix transpose process. By adoption of the dual-mode 8 access address calculation method provided by the invention, the real number matrix transpose execution period can be shortened by single-word dual-mode 8 access address calculation; and the imaginary number matrix transpose execution period can be shortened by double-word dual-mode 8 access address calculation.

Description

technical field [0001] The invention relates to the technical field of digital signal processors, in particular to a dual-mode 8-access address calculation method. Background technique [0002] One of the advantages of DSP compared with general-purpose CPU is that it has specially optimized complex arithmetic and logic operations. Matrix transposition operation belongs to arithmetic and logic operations and is widely used in digital image processing. [0003] The matrix transposition process includes reading the pre-transposed data in the memory unit in a certain order, and then rewriting the transposed data into the memory unit in a corresponding order. When a general-purpose CPU solves the matrix transposition problem, the reading and writing sequence used is to read multiple matrix units in the order from left to right and from top to bottom, and then in the order from top to bottom and from left to right write back. This kind of reading and writing sequence will genera...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/02
Inventor 胡孔阳李岩胡海生贾光帅王媛刘小明
Owner CHINA ELECTRONIC TECH GRP CORP NO 38 RES INST