A Packed Layout Method for Adders

Abstract

The invention relates to a method for packing and deploying adders. The method includes the steps of: identifying the design mode of the adders and other packageable modules in a design of a user; then packing the adders and other packageable modules into one macro block; and disposing the macro block in a logic unit with a fast physical connection line. According to the invention, the design mode of the user can be matched through a usage mode according to the inherent fast line resource of a chip; and after the design mode of the user is matched, the line routing resources used by the adders and other modules are reduced, thereby reducing usage of line routing resources and also reducing the time delay.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a packing and layout method of an adder. Background technique [0002] Currently, in Field Programmable Gate Array (Field Programmable Gate Array, FPGA) applications, integrated circuits are required to have a programmable or configurable interconnection network, and logic gates are connected to each other through the configurable interconnection network. FPGAs, functioning as stand-alone chips or as a core part of a system, have been widely used in a large number of microelectronic devices. The definition of FPGA logic gate in a broad sense not only refers to simple NAND gates, but also refers to logic units of combinational logic and sequential logic with configurable functions or logic blocks composed of multiple logic units interconnected. [0003] There is a short-distance physical connection on the chip hardware, and the delay is short, which belongs to the lev...

AI Technical Summary

Problems solved by technology

However, due to the limitations of the algorithm, it is often impossible to find all the optimal solutions.

[0004] At present, the industry has not proposed a good guarantee to solve the problem of extracting a usage mode to match the user's design mode based on the inherent fast line resources of the chip.

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