43results about How to "Save wiring resources" patented technology

This invention provides a device for taking a two- dimensional fast DCT transform or a two -dimensional fast IDCT transform to the image data composed of 8X8 sub-block. Takes example for one dimensional DCT transform to 8X8 sub-block: the transform device comprises: the control circuit; the input deposit circuit; the butterfly operation circuit; the parallel/serial conversion circuit; table look up operation circuit; the output deposit circuit. The invention adopts the design philosophy that is to replace the multiply operation by look up table, so it need only once butterfly operation, 24 adder, 0 multiplying to complete once DCT. The design philosophy using the pipeline greatly increases the operating speed. The data can be inputted consecutively, the operation result can be gotten at each clock period. The invention is adapted to implement by using FPGA, the resource requirement saves above 30% than current structure. It can be applied in various image compression, especially in MPEG, H.26X format data that makes high requirement for the compression speed and quality.

The invention relates to a random neural network hardware realization apparatus. The apparatus comprises an input layer, a hidden layer and an output layer, wherein the input layer consists of m input neurons I, each input neuron I comprises a random number converter A, and after an input vector passes through the random number converter A, a random data sequence I is output; the hidden layer consists of s hidden neurons J, each hidden neuron J comprises a random number converter B, a random function generator and a definite number converter C, a parameter code stream passes through the random number converter B, is aligned to the random data sequence and passes through the random function generator, so a random data sequence II is obtained, and the random number sequence II passes through the definite number converter C and a definite number I is output; the output layer consists of n output neurons K, each output neuron K comprises a definite number converter D and a linear function processor, and a parameter code stream II passes through the definite number converter D, is aligned to the definite number and passes through the linear function processor, so an object vector is output. According to the apparatus, hardware logic and wiring resources can be greatly reduced, circuit cost and power consumption can be reduced, the network operation precision is high, and the fitting capability of training samples is enhanced.

The invention relates to an artificial neural network hardware implementation device based on probability calculation. The artificial neural network hardware implementation device based on probability calculation comprises input, intermediate and output modules. The input module is formed by I input neurons, and the input neurons receive first data and output a first random data sequence; the intermediate module is formed by J intermediate neurons, and the intermediate neurons receive the first random data/parameter sequence and output a second random sequence; and the output module is formed by K output neurons, and the output neurons receive the second random data/parameter sequence and output the second data, wherein I, J and K are integers greater than or equal to 1. The output end of the input neurons is connected with the input end of the intermediate neurons, the output end of the intermediate neurons is connected with the input end of the output neurons, and a complete or partial connection mode is adopted. The first and second random data sequences and the first and second random parameter sequences are expressed by the probability values of 0 or 1 appearing in the data sequences within a period of time. According to the neural network device, hardware logic and wiring resources can be greatly reduced, and circuit cost and power consumption can be reduced so that implementation of a super-large-scale neural network through small and medium-sized circuits is enabled to be possible.

The invention relates to a method for packing and deploying adders. The method includes the steps of: identifying the design mode of the adders and other packageable modules in a design of a user; then packing the adders and other packageable modules into one macro block; and disposing the macro block in a logic unit with a fast physical connection line. According to the invention, the design mode of the user can be matched through a usage mode according to the inherent fast line resource of a chip; and after the design mode of the user is matched, the line routing resources used by the adders and other modules are reduced, thereby reducing usage of line routing resources and also reducing the time delay.

The invention provides a noise processing method and a circuit after a noise processing process. The circuit after the noise processing process comprises at least two disturbed lines and at least one disturbing line. The number of parallel lines among the at least three line does not exceed two. Parallel portions exist between the disturbed lines and the disturbing line. Common parallel portions exist between the disturbed lines. The width of a gap between the common parallel portions is wider than or equal with a sum value of two times the width of a minimum line gap and the width of the line.

The invention relates to a method and a circuit for transmitting data among modules in a chip of an integrated circuit by a single-wire bus, and aims to solve the problems that the wiring resources are increased, the design flexibility is poor, and the manpower and material cost are increased because of transmitting the data among the modules in the chip of the conventional integrated circuit through a multi-wire bus. The method comprises the following steps of (1) performing Huffman coding on the data to be transmitted in the modules on the chip, and storing the coded data to a transmitting register; (2) transmitting the data in the transmitting register to an acquisition register through the single-wire bus; and (3) performing Huffman decoding on the data in the acquisition register, and extracting effective data for the module to receive data to use. The circuit mainly comprises a Huffman coder, the transmitting register, the acquisition register and a Huffman decoder. By the method and the circuit, least wiring resources are occupied; the transmission mode is flexible; the data can be transmitted and received at any time; a transmission protocol is simple; complex frame structure and packaging design are not required; and the circuit is simple in structure and easy to realize and has no special requirement on hardware.

The invention discloses a method for planning the size of the trunk of clock meshes of an integrated circuit board. The method for planning the size of the trunk of the clock meshes of the integrated circuit board comprises the steps that (1) an arranged design is longitudinally and horizontally zoned evenly to obtain multiple strip-shaped areas; (2) the priorities of the strip-shaped areas are ranked according to the number of loads of the strip-shaped areas, wherein the larger the number of the loads of a strip-shaped area is, the higher the priority of the strip-shaped area is; (3) a single mesh trunk is virtually added to each longitudinal or horizontal strip-shaped area correspondingly in accordance with the order from the highest priority to the lowest priority, and the line capacitance and the clock offset range of the whole meshes are estimated every time one mesh trunk is virtually added until the mesh trunks are added to all the strip-shaped areas; (4) an overall mesh size which can guarantee that the estimated range clock offset range is within a clock offset value range which is assigned by a user and the line capacitance is the smallest serves as a final planning result. The method for planning the size of the trunk of the clock meshes of the integrated circuit board has the advantages that the clock wiring length is small, wiring resources are saved, the clock mesh power consumption caused by the line capacitance is low, the expansibility is good, and the clock line capacitance or the power consumption can be minimized on the premise that indexes of clock offset are obtained.