39 results about "Interneuron" patented technology

Provided herein are compositions and methods for disrupting at least one reward-related behavior in an individual through the use of light-responsive opsin proteins used to control the polarization state of the cholinergic intemeurons of the nucleus accumbens or the striatum.

Methods and systems for generating MGE precursor cells in vitro as well as compositions of enriched MGE precursor cells are provided. The methods and systems provide efficient production of MGE precursors. The methods and systems disclosed herein provide functional MGE precursors which differentiate into functional GABAergic interneurons.

The present invention relates to methods of isolating a purified or enriched population of cortical or striatal immature interneuron progenitor cells and the isolated purified or enriched population of immature interneuron progenitor cells. Methods of treating a condition mediated by a loss or deficiency of interneuron function using the purified or enriched population of immature interneuron progenitor cells are also disclosed.

The invention relates to in vitro methods for differentiating mammalian pluripotent stem cells into cells displaying a neuronal phenotype, more particularly into cortical-type neurons including inter alia pyramidal neurons and cortical inhibitory interneurons. The invention further encompasses so-obtained neuronal cells and cell population, compositions comprising such, and further uses of said neuronal cells and cell population.

Restoration or increase of inhibitory interneuron function in vivo is achieved by transplantation of MGE cells into the brain. Compositions containing MGE cells are provided as are uses to treat various diseases characterised by abnormal inhibitory interneuron function or in cases where increase inhibition may ameliorate neural circuits that are abnormally activated.

The invention relates to a GABAergic neuron conditional knockout gene PGC-1 alpha mouse model and a construction method thereof and belongs to the field of animal models and application thereof. The construction method includes the steps that a PGC-1 alpha <flox / flox> mouse is obtained in the first place; then, a PGC-1 alpha <flox / +> is mated with a C57BL / 6J, and the PGC-1 alpha <flox / +> is obtained, then the PGC-1 alpha <flox / +> and the C57BL / 6J are mated with a Dlx5 / 6<Cre-IRES-EGFP> mouse, and the full knockout D1x5 / 6< Cre-IRES-EGFP >, PGC-1 alpha <flox / flox>, semi knockout D1x5 / 6< Cre-IRES-EGFP > and a PGC-1 alpha <flox> mouse are obtained; as a result, a gene knockout mouse on GABAergic internuncial neuron conditional knockout PGC-1 alpha is prepared, and a credible animal model is provided for mechanism research on neurodevelopment and neurodegenerative diseases.

The invention relates to an artificial neural network hardware implementation device based on probability calculation. The artificial neural network hardware implementation device based on probability calculation comprises input, intermediate and output modules. The input module is formed by I input neurons, and the input neurons receive first data and output a first random data sequence; the intermediate module is formed by J intermediate neurons, and the intermediate neurons receive the first random data / parameter sequence and output a second random sequence; and the output module is formed by K output neurons, and the output neurons receive the second random data / parameter sequence and output the second data, wherein I, J and K are integers greater than or equal to 1. The output end of the input neurons is connected with the input end of the intermediate neurons, the output end of the intermediate neurons is connected with the input end of the output neurons, and a complete or partial connection mode is adopted. The first and second random data sequences and the first and second random parameter sequences are expressed by the probability values of 0 or 1 appearing in the data sequences within a period of time. According to the neural network device, hardware logic and wiring resources can be greatly reduced, and circuit cost and power consumption can be reduced so that implementation of a super-large-scale neural network through small and medium-sized circuits is enabled to be possible.