DCT rapid changing structure

Abstract

This invention provides a device for taking a two- dimensional fast DCT transform or a two -dimensional fast IDCT transform to the image data composed of 8X8 sub-block. Takes example for one dimensional DCT transform to 8X8 sub-block: the transform device comprises: the control circuit; the input deposit circuit; the butterfly operation circuit; the parallel/serial conversion circuit; table look up operation circuit; the output deposit circuit. The invention adopts the design philosophy that is to replace the multiply operation by look up table, so it need only once butterfly operation, 24 adder, 0 multiplying to complete once DCT. The design philosophy using the pipeline greatly increases the operating speed. The data can be inputted consecutively, the operation result can be gotten at each clock period. The invention is adapted to implement by using FPGA, the resource requirement saves above 30% than current structure. It can be applied in various image compression, especially in MPEG, H.26X format data that makes high requirement for the compression speed and quality.

Description

technical field [0001] The present invention relates to the FPGA-based DCT / IDCT transform structure of discrete cosine transform (hereinafter referred to as "DCT") and inverse discrete cosine transform (hereinafter referred to as "IDCT") used in information compression technologies such as image signal processing, and in particular to The image data composed of multiple 8×8 sub-blocks is subjected to two-dimensional DCT operation or two-dimensional IDCT transformation structure. Background technique [0002] With the development of microelectronics technology, the development of electronic information products has two obvious characteristics: one is the increasing complexity of products, and the other is the tight time limit for products to go to market. In response to this situation, Field Programmable Logic Devices (FPLDs) have emerged, of which Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs) are the most widely used. [0003] Similar...

AI Technical Summary

Problems solved by technology

[0053] From the entire calculation process above, we can find that although the use of parity symmetry reduces the amount of calculation, but because of the use of multiple butterfly calculation structures with irregular wiring, not only the area of ​​the entire circuit is large, it consumes a lot of wiring resources, but also because Contains multiple multiplication and addition and subtraction operations, so the amount of calculation is still too large

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