Method for debugging logic system design, simulator and storage medium

Abstract

The invention provides a method for debugging logic system design, a simulator and a storage medium. The method comprises the following steps: cutting the logic system design into at least two blocks,wherein the at least two blocks comprise a target block; acquiring runtime information of a plurality of excitation signals of the target block; determining a circuit structure of the target block; and determining runtime information of output signals of a plurality of components of the target block according to the runtime information of the plurality of excitation signals of the target block and the circuit structure of the target block.

Description

technical field [0001] The present disclosure relates to the field of circuit technology, and in particular to a method for debugging logic system design, an emulator, and a storage medium. Background technique [0002] The emulator can prototype (prototype) and debug a logic system design including one or more modules. The logic system design may be, for example, a design for an application specific integrated circuit (Application Specific Integrated Circuit, ASIC for short) or a system-on-chip (System-On-Chip, SOC for short). Therefore, the logic system design tested in the emulator can also be called the Device Under Test (DUT for short). The emulator can emulate the device under test through one or more configurable components (for example, Field Programmable Gate Array (Field Programmable Gate Array, FPGA for short)), including performing various operations of the device under test, so that the Test and verify the functionality of each module of the device under test ...

AI Technical Summary

Problems solved by technology

However, each module of the device under test usually includes millions (or even more) of signals that need to be probed, and it would take a lot of time and resources to probe all the signals

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