A Planning Method for Backbone Dimensions of Integrated Circuit Clock Grid

Abstract

The invention discloses a method for planning the size of the trunk of clock meshes of an integrated circuit board. The method for planning the size of the trunk of the clock meshes of the integrated circuit board comprises the steps that (1) an arranged design is longitudinally and horizontally zoned evenly to obtain multiple strip-shaped areas; (2) the priorities of the strip-shaped areas are ranked according to the number of loads of the strip-shaped areas, wherein the larger the number of the loads of a strip-shaped area is, the higher the priority of the strip-shaped area is; (3) a single mesh trunk is virtually added to each longitudinal or horizontal strip-shaped area correspondingly in accordance with the order from the highest priority to the lowest priority, and the line capacitance and the clock offset range of the whole meshes are estimated every time one mesh trunk is virtually added until the mesh trunks are added to all the strip-shaped areas; (4) an overall mesh size which can guarantee that the estimated range clock offset range is within a clock offset value range which is assigned by a user and the line capacitance is the smallest serves as a final planning result. The method for planning the size of the trunk of the clock meshes of the integrated circuit board has the advantages that the clock wiring length is small, wiring resources are saved, the clock mesh power consumption caused by the line capacitance is low, the expansibility is good, and the clock line capacitance or the power consumption can be minimized on the premise that indexes of clock offset are obtained.

Description

technical field [0001] The present invention relates to the field of integrated circuit (Integrated Circuit, hereinafter referred to as IC) design automation in the field of microelectronics technology, in particular to a method for planning the backbone size of an integrated circuit (IC) clock grid (ClockMesh). Background technique [0002] Such as figure 1 As shown, at present, semi-custom digital integrated circuits (ICs) generally start with the logic design of digital logic circuits using Hardware Description Language (Hardware Description Language, HDL), through front-end simulation, logic synthesis to generate gate-level netlists, etc., until the completion of the circuit Layout routing, timing and manufacturability convergence verification, and finally the chip product formed by tape-out. The stage after the gate-level netlist is generated by logic synthesis belongs to the back-end design. The main steps of the back-end design include floor plan and layout and optim...

AI Technical Summary

Problems solved by technology

For designs with small scale or less tight clock constraints, Clock Tree Synthesis (CTS for short) can fully meet the needs of users. The number of stages of the clock tree is large, and the non-common path is long, resulting in relatively large clock delay and deviation. Nowadays, ultra-deep sub-micron technology such as 45nm and below makes the impact of on-chip error (OnChipVariation, hereinafter referred to as OCV) more and more obvious. The existence of the common path further increases the clock skew

Mesh-type clock structure is the best choice to solve this kind of problem. Both tools mentioned above provide mesh-type clock synthesis solutions, but compared with CTS, Clock Mesh Synthesis (ClockMeshSynthesis, hereinafter referred to as CMS) requires users to determine more parameters, such as the number of grid backbones, wiring layers, width, placement, etc., and the degree of automation is very low

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