An integrated circuit and method for detection of malicious code in a first level instruction cache

A high-speed cache, integrated circuit technology, applied in the field of malicious code

Active Publication Date: 2017-08-18
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the ability to execute code without accessing the L2 cache may allow an adversary to replace harmless code that uses the L2 cache with malicious / corrupt code that does not use the L2 cache without the replacement being detected

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  • An integrated circuit and method for detection of malicious code in a first level instruction cache
  • An integrated circuit and method for detection of malicious code in a first level instruction cache
  • An integrated circuit and method for detection of malicious code in a first level instruction cache

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Embodiment Construction

[0016] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0017] see figure 2 and 3 , an aspect of the invention may reside in an integrated circuit 210 comprising: a processor 220, a first-level instruction cache 230 having a first storage capacity, and a second-level instruction cache 230 having a second storage capacity greater than the first storage capacity Buffer memory 240 . A first level instruction cache is coupled between the processor and the second level cache and is configured to store a subset of the instructions stored in the second level cache. The second level cache is coupled between the first level instruction cache and the external memory 250 and is configured to store a subset of the data and instructions stored in the external memory. The processor is configured to execut...

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Abstract

An integrated circuit may comprise a processor, a first level instruction cache having a first storage capacity, and a second level cache having a second storage capacity that is larger than the first storage capacity. The first level instruction cache is configured to store a subset of instructions stored in the second level cache. The second level cache is configured to store a subset of data and instructions stored in an external memory. The processor executes an inner loop of a detection routine and monitors an execution time of the inner loop to detect malicious code in the first level instruction cache. A total number of detection routine instructions is larger than the first storage capacity. The inner loop requires fetching of detection routine instructions from the second level cache, and an execution number of instructions executed during execution of the inner loop is smaller than the first storage capacity.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS [0002] This application claims priority to and is entitled to US Nonprovisional Application Serial No. 14 / 493,306, filed September 22, 2014, with the US Patent Office, which is incorporated herein by reference in its entirety. technical field [0003] The present invention generally relates to detecting malicious code associated with do-not-cache attacks. Background technique [0004] Many computing environments include instructions that fetch one or more instructions directly from RAM. These instructions are not stored in the second level (L2) cache, but instead are copied directly into the smaller and faster first level (L1) instruction cache. Typically, bypassing the L2 cache is a benign operation. However, the ability to execute code without accessing the L2 cache may allow an adversary to replace harmless code that uses the L2 cache with malicious / corrupt code that does not use the L2 cache without the replacement bein...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/0811G06F12/0875G06F12/0897G06F12/14
CPCG06F12/0811G06F12/0875G06F12/0897G06F12/14G06F21/563G06F2212/1052G06F2221/033
Inventor B·M·雅各布松
Owner QUALCOMM INC
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