High-precision array analog-to-digital convertor applicable to CMOS image sensor

Abstract

The invention discloses a high-precision array analog-to-digital convertor applicable to a CMOS image sensor, and belongs to the technical field of design of analog circuits. The high-precision array analog-to-digital convertor comprises a sampling holding circuit, a comparator, a digital-to-analog convertor, a successive approximation register and a digital error correction circuit; a full differential structure is adopted in the analog-to-digital convertor; input signals are output to a capacitor array top plate through the sampling holding circuit, and simultaneously, input into the input end of the comparator; the output end of the comparator is connected with the successive approximation register; and the successive approximation register controls and stores a capacitor array according to a comparator result, and outputs the capacitor array to the digital error correction circuit, so that finally binary output is obtained. By means of the high-precision array analog-to-digital convertor disclosed by the invention, the capacitor array is divided into three sections of capacitor arrays, wherein each section of capacitor array is designed by adoption of a non-binary redundant capacitor architecture; the high-precision array analog-to-digital convertor has a certain tolerance for comparative errors due to incomplete establishment of circuits, jitter and noise of reference voltage and the metastable state of a dynamic comparator; the dynamic comparator is also adopted; quiescent current does not exist; and thus, the power consumption of the whole circuit is effectively reduced.

Description

technical field [0001] The invention belongs to the technical field of analog circuit design, in particular to an array successive approximation analog-to-digital converter applied to a CMOS image sensor. Background technique [0002] With the rapid development of CMOS technology, various systems have higher and higher requirements for analog-to-digital converters. At present, the development trend of ADC mainly has the following two directions: [0003] 1. Develop in the direction of low power consumption and small area [0004] With the increasing scale of integrated circuits, power consumption has become an important indicator for comparing chips with similar performance. Facing the development of CMOS technology, the technology of CMOS has been continuously improved, from a few um to the current tens of nm, and at the same time, the power supply voltage required by each module is also continuously reduced. Continuously improve power consumption through power sleep mod...

AI Technical Summary

Problems solved by technology

The successive approximation analog-to-digital converter (SAR ADC) usually adopts a charge redistribution structure. Since the total unit capacitance of the capacitive successive approximation analog-to-digital converter is exponentially related to the accuracy of the analog-to-digital converter (ADC), for higher For a successive approximation analog-to-digital converter (SAR ADC) with high precision, the total amount of capacitance and chip area will increase sharply, and the dynamic power consumption consumed when switching capacitors will also increase accordingly.

[0007] Therefore, for a high-precision capacitive successive approximation analog-to-digital converter, it is usually necessary to use a large capacitor, which results in: large charge and discharge power consumption, large area required for making chips, and increased economic costs.

At the same time, due to the improvement of the accuracy of the analog-to-digital converter, capacitance mismatch, comparator comparison error, etc. have a greater impact on the analog-to-digital converter, which limits the design of the successive approximation analog-to-digital converter

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